reg_file.vhd

来自「这个是Xilinx编程的源码」· VHDL 代码 · 共 62 行

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--  entity       = register file   --
--  version      = 1.0              --
--  last update  = 20/06/05         --
--  author       = Jose Nunez       --
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-- register file stores 5 numbers


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity register_file is
port
(
	clk : in std_logic;
	data_in : in std_logic_vector(3 downto 0);
	srd : in std_logic_vector(2 downto 0);
	enwr : in std_logic;
	swr : in std_logic_vector(2 downto 0);
	clear : in std_logic; -- general asyncronous reset
	reset : in std_logic; --general syncronous reset
	new_sort : in std_logic; -- start sorting new numbers
	data_middle  : out std_logic_vector(3 downto 0);
	data_out : out std_logic_vector(3 downto 0)
);

end register_file;

architecture struct of register_file is

-- one 4-bit register

component register4
port
(	
	clk : in std_logic;
	data_in : in std_logic_vector(3 downto 0);
	enwr : in std_logic;
	reset : in std_logic;
	new_sort : in std_logic;
	clear : in std_logic;
	data_out : out std_logic_vector(3 downto 0)
);
end component;

-- add signals here

begin

-- add code here



end struct;  -- end of architecture