timer_set.vhd

实现一个简单的电子钟

----------------------------- timer_set.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


--------------------------------------------------------------实体
entity  timer_set is

port(
    cp:    in std_logic;
    segout:   out std_logic_vector(7 downto 0);
    selout : out std_logic_vector(5 downto 0);
    numout: out  std_logic_vector(3 downto 0);
    key :     in  std_logic_vector(2 downto 0)
     );
end timer_set;
--------------------------------------------------------------部分

 
architecture a of timer_set is    
     
 --60进制计数器组件
component counter60

    port(  cp :  in    std_logic;
          bin :  out   std_logic_vector(5 downto 0);
             s:  in    std_logic;
           clr:  in    std_logic;
            ec:  in    std_logic;
          cy60:  out   std_logic
);
end component;

 --申明24进制计数器
component counter24          
    port( cp :  in   std_logic;
          bin:  out  std_logic_vector(5 downto 0);
            s:  in   std_logic;
          clr:  in   std_logic;
           ec:  in   std_logic;
         cy24:  out  std_logic
);
end component;

signal  bin: std_logic_vector(5 downto 0); --数据输出
signal  dbs: std_logic_vector(5 downto 0); 
signal  dbm: std_logic_vector(5 downto 0);
signal  dbh: std_logic_vector(5 downto 0);
signal  enb: std_logic_vector(2 downto 0);

signal  sec :std_logic;
signal  bcd: std_logic_vector(7 downto 0);
signal  clr :std_logic;
signal  cys,cym,cyh :std_logic;
signal  s: std_logic_vector(2 downto 0);
signal  num: std_logic_vector(3 downto 0);
signal  seg: std_logic_vector(6 downto 0);
signal  sel: std_logic_vector(5 downto 0);
signal  sample,dly_out,diff: std_logic;
signal  state: std_logic_vector(1 downto 0); 


signal match:std_logic;
signal   glitter:std_logic;
begin
    connection:block
    signal adj,ecs,ecm,ech,sc:std_logic;

    begin
             u1: counter60 port map(cp,dbs,enb(0),clr,ecs,cys);
             u2: counter60 port map(cp,dbm,enb(1),clr,ecm,cym);
             u3: counter24 port map(cp,dbh,enb(2),clr,ech,cyh);
 
             clr<=not key(0);
             sc<=state(1) and state (0);
             adj<=sec and (not sc) and key(1);-------------------------------------
             ecs<=(sec and sc) or(adj and  state(1)  and not state(0));
             ecm<=(cys and sc) or(adj and not state(1)  and  state(0));
             ech<=(cym and sc) or(adj and not state(1)  and not state(0));
             selout <=sel;

             gen: for i in  0 to 6   generate
                segout(i)<=seg(i)and(sc or ( glitter or not match));--------------------------------------

    end generate;
          segout(7)<='0';
           numout<=num;

    end block connection;

    free_counter:block
    signal  q: std_logic_vector(24 downto 0); 
    signal dly,sdly:std_logic;
    begin
     process(cp)---------------------------------------
begin
 if cp'event and cp='1' then
      dly<=q(21);
      sdly<=q(14);
      q<=q+1;
    end if;
  end  process;-------------------------------------------
  
glitter<=q(21);--------------------------------------------------
sec<=q(21) and not dly;
s<=q(15 downto 13);

sample<=q(14) and not sdly;

 sel<="000001" when s=0 
      else
      "000010" when s=1 
      else
      "000100" when s=2 
      else
      "001000" when s=3 
      else
      "010000" when s=4 
      else
      "100000" when s=5 
      else
      "000000";

   enb<="001" when(s=0 or s=1) else
        "010" when(s=2 or s=3) else
        "100" when(s=4 or s=5) else
        "000" ;

   bin<=dbs when enb="001" else
        dbm when  enb="010" else
       dbh when enb="100" else
       "000000";

   match<='1' when((s=0 or s=1) and state="10") else---------------------------match
         '1' when((s=2 or s=3) and state="01") else
         '1' when((s=4 or s=5) and state="00") else
         '0';

       end block free_counter;

     binary_bcd:block
        begin
         bcd<="00000000" when bin=0 else
              "00000001" when bin=1 else
              "00000010" when bin=2 else
              "00000011" when bin=3 else
              "00000100" when bin=4 else
              "00000101" when bin=5 else
              "00000110" when bin=6 else
              "00000111" when bin=7 else
              "00001000" when bin=8 else
              "00001001" when bin=9 else
              "00010000" when bin=10 else
              "00010001" when bin=11 else
               "00010010" when bin=12 else
               "00010011" when bin=13 else
               "00010100" when bin=14 else
               "00010101" when bin=15 else
               "00010110" when bin=16 else
               "00010111" when bin=17 else
               "00011000" when bin=18 else
               "00011001" when bin=19 else
                "00100000" when bin=20 else
                "00100001" when bin=21 else
                "00100010" when bin=22 else
                "00100011" when bin=23 else
                "00100100" when bin=24 else
                "00100101" when bin=25 else
                "00100110" when bin=26 else
                "00100111" when bin=27 else
                "00101000" when bin=28 else
                "00101001" when bin=29 else
                "00110000" when bin=30 else
                "00110001" when bin=31 else
                "00110010" when bin=32 else
                "00110011" when bin=33 else
                "00110100" when bin=34 else
                "00110101" when bin=35 else
                "00110110" when bin=36 else
                "00110111" when bin=37 else
                "00111000" when bin=38 else
                "00111001" when bin=39 else
                "01000000" when bin=40 else
                "01000001" when bin=41 else
                "01000010" when bin=42 else
                "01000011" when bin=43 else
                "01000100" when bin=44 else
                "01000101" when bin=45 else
                "01000110" when bin=46 else
                "01000111" when bin=47 else
                "01001000" when bin=48 else
                "01001001" when bin=49 else
                "01010000" when bin=50 else
                "01010001" when bin=51 else
                "01010010" when bin=52 else
                "01010011" when bin=53 else
                "01010100" when bin=54 else
                "01010101" when bin=55 else
                "01010110" when bin=56 else
                "01010111" when bin=57 else
                "01011000" when bin=58 else
                "01011001" when bin=59 else
                "00000000";

        end block binary_bcd;

       select_bcd:block
          begin
             num<=bcd(3 downto 0) when(s=0 or s=2 or s=4) else
                 bcd(7 downto 4);

        end  block select_bcd;

    seven_segment:block

  begin
        seg<="0111111" when num=0 else
             "0000110" when num=1 else
             "1011011" when num=2 else
             "1001111" when num=3 else
             "1100110" when num=4 else
             "1101101" when num=5 else
             "1111101" when num=6 else
             "0000111" when num=7 else
             "1111111" when num=8 else
             "1101111" when num=9 else
             "1110111" when num=10 else
             "1111100" when num=11 else
             "0111001" when num=12 else
             "1011110" when num=13 else
             "1111001" when num=14 else
             "1110001" when num=15 else
             "0000000";

             

  end block seven_segment;

   debounce:block

    signal d0,d1,s,r,dly,ndly:std_logic;
   begin
   process(cp)---------------------------------------------------
      begin
     if cp'event and cp='1' then
       if sample='1' then
           d1<=d0;
         d0<=key(2);
                  s<=d0 and d1;
                  r<=not d0 and not d1;
           end if;
              end if;
          end process;---------------------------------------------
 dly<=r nor ndly;
 ndly<=s nor dly;
  dly_out<=dly;

  end block debounce;


    differential:block
       signal d1,d0:std_logic;
  
begin
     process(cp)----------------------------------------
  begin
if cp'event and cp='1' then
 d1<=d0; d0<=dly_out;
end if;

end process;------------------------------------------

diff<=d0 and not d1;

 end block differential;


 timerset :block


  signal q:  std_logic_vector( 2 downto 0);
   signal set,ec: std_logic;
    begin 
 process(cp)-------------------------------------------------

   begin
          if set='1' then 
             q<="011";

              elsif (cp'event and cp='1') then
                  if ec='1'then
                        q<=q-1;
                  end if;
          end if;
    end process;
 set<='1' when q=7 else
  '0';
 ec<=diff and key(2);
 state<=q(1 downto 0);
  end block timerset;
 end a;