pingpanggame.vhd

用max+plusII编写的vhdl程序 乒乓球游戏机

LIBRARY	IEEE;
USE	IEEE.STD_LOGIC_1164.ALL;
USE	IEEE.STD_LOGIC_ARITH.ALL;
USE	IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY	pingpanggame	IS
PORT(clk_4mhz:IN	STD_LOGIC;
	playr:IN	STD_LOGIC;
	playl:IN	STD_LOGIC;
	judge:IN	STD_LOGIC;
	clr:IN	STD_LOGIC;
	led:OUT	STD_LOGIC_VECTOR(8 DOWNTO 0);
	tclr:IN	STD_LOGIC;
	scan:OUT STD_LOGIC_VECTOR(5 downto 0);
	displaycode:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END pingpanggame;

ARCHITECTURE	play	OF	pingpanggame	IS

COMPONENT clockmake                                 
    PORT (CLK		: IN STD_LOGIC; 
          CLK_DSP	:OUT   STD_LOGIC; 
          CLK_1HZ 	:OUT STD_LOGIC
          );
END COMPONENT;

COMPONENT	playandled	
PORT(
	clk:	IN	STD_LOGIC;
	playr:	IN	STD_LOGIC;
	playl:	IN	STD_LOGIC;
	judge:	IN	STD_LOGIC;
	led:	OUT	STD_LOGIC_VECTOR(9	DOWNTO	1);
	playrloss:OUT STD_LOGIC;
	playlloss:OUT STD_LOGIC
	);
END	COMPONENT; 

COMPONENT display	
PORT( bcdin:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	displaycode:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END	 COMPONENT;

COMPONENT dataget  
PORT(datain:IN	STD_LOGIC_VECTOR(23 DOWNTO 0);
	clk_dsp:IN  STD_LOGIC;
	scan:	OUT	STD_LOGIC_VECTOR(5	DOWNTO	0);
	bcdout: OUT	STD_LOGIC_VECTOR(3	DOWNTO	0)
	);
END COMPONENT;

COMPONENT datacontrol 
PORT(
	clk_1hz:IN STD_LOGIC;
	clr:IN STD_LOGIC;
	tclr:IN STD_LOGIC;
	playrloss:IN STD_LOGIC;
	playlloss:IN STD_LOGIC;
	data:OUT STD_LOGIC_VECTOR
	);
END COMPONENT;
SIGNAL clk_1hz:STD_LOGIC;
SIGNAL clk_dsp:STD_LOGIC;
SIGNAL bcdin:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL	playrloss:STD_LOGIC;
SIGNAL	playlloss:STD_LOGIC;
SIGNAL  data:STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL  bcdout:	STD_LOGIC_VECTOR(3	DOWNTO	0);
-------------------------------------------------
-------------------------------------------------
BEGIN
------------------------------------------------------
U1: clockmake PORT MAP(CLK=>CLK_4MHZ,CLK_DSP=>CLK_DSP,CLK_1HZ=>CLK_1HZ);
-----------------------------------------------------
U5:playandled PORT MAP(playl=>playl,playr=>playr,judge=>judge,clk=>clk_1hz,
							led=>led,playlloss=>playlloss,playrloss=>playrloss);
------------------------------------------------------------------------------------
U6:datacontrol PORT MAP(clk_1hz=>CLK_1HZ,clr=>clr,tclr=>tclr,playrloss=>playrloss,
							playlloss=>playlloss,data =>data );
---------------------------------------------------------------------------------------
U7:dataget PORT MAP(datain =>data ,clk_dsp=>clk_dsp,scan =>scan ,bcdout =>bcdout );
-----------------------------------------------------------------------------------
U8:display PORT MAP(bcdin =>bcdout ,displaycode=>displaycode );
----------------------------------------------------------------------------------
END play;