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找到约 10,000 项符合
Logic Analyzer 的代码
counter24.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity counter24 is
port(
clk,clr:in std_logic;
cout:out std_logic;
low,high:out st
circuit.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.numeric_std.ALL;
ENTITY circuit IS
-- Declarations
PORT(
clk : IN std_logic;
reset : IN std_logic;
fmin : IN s
txmit_tb.vhd
-- VHDL Test Bench Created from source file txmit.vhd -- 16:58:29 04/12/2000
--
-- Notes:
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_v
fenpin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fenpin is
port(clk : in std_logic;
clk1hz:out std_logic);
end fenpin;
architecture one of fenpin
dplay.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dplay is
port(stop: in std_logic;
clk: in std_logic;
segin: in std_logi
traffic_lights.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity traffic_lights is
port(clk: in std_logic;------1khz;
stop:in std_logic;
adr:out std_logic_vector(1
加法器源程序.vhd
------------------------------------------------------------------------
-- Single-bit adder
------------------------------------------------------------------------
library IEEE;
use IEEE.std_log
加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
相应加法器的测试向量（test bench).vhd
-- download from: www.pld.com.cn & www.fpga.com.cn
entity testbench is
end;
------------------------------------------------------------------------
-- testbench for 8-bit adder
------------
alaw_l_nl.vhd
library ieee;
use ieee.std_logic_1164.all;
entity alaw_l_nl is
port(
data :in std_logic_vector(12 downto 0); --pcm linear signal
clock :in std_logic; --system clock
fram