alaw_l_nl.vhd

使用VHDL实现通信脉冲编码调制（PCM）中的a律转换

library ieee;
use ieee.std_logic_1164.all;

entity alaw_l_nl is
	port(
			data			:in			std_logic_vector(12 downto 0);	--pcm linear signal
			clock			:in			std_logic;						--system clock
			frame			:in			std_logic;						--frame synchronous signal
			ebi				:in			std_logic;						--enable even bit(a-law) inversion.1:inverted;0:not inverted
			dataq			:out		std_logic);						--output overlap signal
end alaw_l_nl;

architecture structure of alaw_l_nl is
	COMPONENT alaw_13_8
		PORT(
			data			:in			std_logic_vector(12 downto 0);	--linear signal 
			frame			:in			std_logic;						--frame synchronous signal
			dataq			:out		std_logic_vector(7 downto 0));	--output nolinear signal
	END COMPONENT;

	COMPONENT alaw_invert
		PORT(
			data			:in			std_logic_vector(7 downto 0);	--pcm nolinear signal
--			frame			:in			std_logic;						--frame synchronous signal
			ebi				:in			std_logic;						--enable even bit(a-law) inversion.1:inverted;0:not inverted
			dataq			:out		std_logic_vector(7 downto 0));	--output inversion signal
	END COMPONENT;

	COMPONENT p_s
		PORT(
			data			:in			std_logic_vector(7 downto 0);	--pcm linear signal
			clock			:in			std_logic;						--clock signal
			frame			:in			std_logic;						--frame signal
			dataq			:out		std_logic);						--output overlap signal
	END COMPONENT;

	signal	data_p_s,data_invert	:std_logic_vector(7 downto 0);
begin
	u1:alaw_13_8
		port map(data	=> data,
				 frame	=> frame,
				 dataq 	=> data_invert);
	u2:alaw_invert
		port map(data	=> data_invert,
--				 frame	=> frame,
				 ebi	=> ebi,
				 dataq 	=> data_p_s);
	u3:p_s
		port map(data	=> data_p_s,
				 clock	=> clock,
				 frame	=> frame,
				 dataq	=> dataq);
end structure;