代码搜索：Logic Analyzer
找到约 10,000 项符合「Logic Analyzer」的源代码
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www.eeworm.com/read/393840/8260476
vhd ddr_data_path.vhd
--
-- LOGIC CORE: DDR Data Path Module
-- MODULE NAME: ddr_data_path()
-- COMPANY: Northwest Logic, Inc.
-- www.nwlogic.com
--
-- R
www.eeworm.com/read/393803/8262805
txt qiangdaqi.txt
LIBRARY IEEE; --状态控制模块
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY zhuangtai IS
PORT (I1, I2, I3, I4: IN STD_LOGIC;
www.eeworm.com/read/393727/8268312
txt 米勒型状态机.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in
www.eeworm.com/read/393358/8294145
vhd msecond.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity msecond is
port(
clk, reset,set : in std_logic;
ensec : out s
www.eeworm.com/read/393358/8294165
vhd second.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity second is
port(
clk, reset ,set : in std_logic;
enmin : out
www.eeworm.com/read/393344/8295555
vhd msecond.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity msecond is
port(
clk, clr ,set : in std_logic;
ensec : o
www.eeworm.com/read/393344/8295561
vhd act.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity act is
port
(
clk, clr: in std_logic;
second,minute,hour : in std_logic_ve
www.eeworm.com/read/293226/8305791
vhd xspfpga.vhd
--------------------------------------------------------------------------------
-- Copyright (c) 2000 by Trenz Electronic.
-- Duenner Kirchweg 77, 32257 Buende, Germany, www.trenz-electronic.de
--
www.eeworm.com/read/293017/8318454
vhd c4240c.vhd
----------------------------------------------------------------------
----------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE
www.eeworm.com/read/392763/8327880
vhd compare.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity compare is
port(ok,clk : in std_logic;--计时时钟
d,e : in std_logic_vector(5 downto 0);--开锁时输入的密码
f: out s