📄 msecond.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity msecond is
port(
clk, reset,set : in std_logic;
ensec : out std_logic;
daout : out std_logic_vector (7 downto 0));
END entity msecond ;
architecture fun of msecond IS
signal count: std_logic_vector( 7 downto 0);
begin
daout <= count;
process ( clk , reset ,set )
begin
if (reset='1') then
count <= "00000000";
elsif (set='0')then
if (clk'event and clk='1') then
if (count(3 downto 0)="1001") then
if (count <"10100000") then
if (count="10011001") then
ensec <='1';
count<="00000000";
else
count<=count+7;
end if;
else
count<="00000000";
end if;
elsif (count < "10100000") then
count <= count+1;
ensec <='0';
else
count<="00000000";
end if;
end if;
end if;
end process;
end fun;
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