📄 act.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity act is
port
(
clk, clr: in std_logic;
second,minute,hour : in std_logic_vector (6 downto 0);
set_clk: in std_logic;
dot: out std_logic;
daout1 : out std_logic_vector( 6 downto 0);
sel1 : out std_logic_vector( 5 downto 0));
end entity act;
architecture fun of act is
signal sel:std_logic_vector( 5 downto 0);
signal count: std_logic_vector ( 2 downto 0);
signal num: std_logic_vector ( 3 downto 0);
signal daout: std_logic_vector ( 6 downto 0);
begin
process ( clk,clr,num)
begin
if (clr ='1') then
count <= "000";
elsif (clk'event and clk='1') then
if ( count = "000") then
if(set_clk='1')then
num<="0000";
else
num<=second(3 downto 0);dot<='0';end if;sel<="000001";
end if;
if( count ="001") then
if(set_clk='1')then
num<="0000";
else
num(3)<='0'; num(2 downto 0)<=second(6 downto 4);dot<='0';end if;sel<="000010";
end if;
if( count ="010") then
num<=minute(3 downto 0);dot<='1';sel<="000100";
end if;
if(count ="011") then
num(3)<='0'; num(2 downto 0)<=minute(6 downto 4);dot<='0';sel<="001000";
end if;
if(count ="100")then
num<=hour(3 downto 0);dot<='1';sel<="010000";
end if;
if(count ="101")then
num(3)<='0'; num(2 downto 0)<=hour(6 downto 4);dot<='0';sel<="100000";
end if;
if(count ="110")then
count<="000";sel<="000000";
end if;
count<=count+1;
end if;
if(num= "0000")then
daout<="0111111";end if;
if(num= "0001")then
daout<="0000110";end if;
if(num= "0010")then
daout<= "1011011";end if;
if(num= "0011")then
daout<="1001111"; end if;
if(num= "0100")then
daout<="1100110"; end if;
if(num= "0101")then
daout<="1101101"; end if;
if(num= "0110")then
daout<="1111101"; end if;
if(num="0111")then
daout<="0000111" ; end if;
if(num= "1000")then
daout<="1111111" ; end if;
if(num="1001")then
daout<="1101111" ;end if;
end process;
sel1<=sel;
daout1<=daout;
end architecture fun;
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