c4240c.vhd

一个通用计数器的VHDL源代码,只要稍做修改

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LIBRARY ieee;
USE     ieee.std_logic_1164.ALL;
USE     ieee.std_logic_unsigned.ALL;


-- Cascadable up/down Decade counter with synchronous reset.

ENTITY c4240c  IS
  PORT (
       clk               : in std_logic;
       reset             : in std_logic;
       qouta              : out   std_logic_vector(15 DOWNTO  0);
       cout               : out  std_logic;
       coutb            :  out std_logic;
       coutc            :  out  std_logic;
       cen               : in std_logic
       
       
  );
END c4240c;

ARCHITECTURE behave of c4240c   is
 signal rega:  std_logic_vector(15  downto  0); 
BEGIN
 
  PROCESS(clk,reset,rega,cen)
   BEGIN
     
  if(clk='1' and clk'event) then
    if (reset='1') then
     rega<="0000000000000000";
    elsif(cen='1') then
      if(rega>=4239) then
       rega<="0000000000000000";
       
       else 
       rega<=rega+1;
       end if;
    else
    null;
    end if;
  else
    null;
  end if;      
     qouta<=rega;


   if(rega=2119 or  rega=0) then
     cout<='1';
   else
     cout<='0';
   end if;

  if( rega=4239) then
     coutb<='1';
   else
     coutb<='0';
   end if;

  if(rega=2119 ) then
     coutc<='1';
   else
     coutc<='0';
   end if;

      
    end process;
    end behave;