qiangdaqi.txt

四人抢答器设计,具有超前抢答显示报警

LIBRARY IEEE;                     --状态控制模块
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY zhuangtai IS
   PORT (I1, I2, I3, I4: IN STD_LOGIC;
     RESET, START, CLK: IN STD_LOGIC;
      LIGHT, SOUND: OUT STD_LOGIC;
      LED1, LED2: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
      sel: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
      C: OUT STD_LOGIC);
END zhuangtai;
ARCHITECTURE zt OF zhuangtai IS
TYPE STATE IS (STATE1, STATE2, state3);
SIGNAL MYSTATE: STATE;
SIGNAL A, B: STD_LOGIC;
signal Q1:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
   PROCESS(RESET,START,I1,I2,I3,I4,MYSTATE,a,b,clk,q1)
     BEGIN
        IF RESET='1' THEN
           MYSTATE<=STATE1;
  LED1<="000"; LED2<="000";
  A<='1'; B<='1'; LIGHT<='0'; sel<="000"; sound<='0';
ELSE IF (CLK'EVENT AND CLK='1') THEN
  CASE MYSTATE IS
    WHEN STATE1=>
    IF START='0' THEN
      IF (I1='1'AND A='1') THEN
        LIGHT<='1'; LED1<="001"; A<='0'; SOUND<='1';
      ELSIF (I2='1'AND A='1') THEN
        LIGHT<='1'; LED1<="010"; A<='0'; SOUND<='1';
       ELSIF (I3='1'AND A='1') THEN
       LIGHT<='1'; LED1<="011"; A<='0'; SOUND<='1';
        ELSIF (I4='1'AND A='1') THEN
       LIGHT<='1'; LED1<="100"; A<='0'; SOUND<='1';
      END IF;
ELSE
     
        MYSTATE<=STATE2; END IF;
IF A='0' THEN MYSTATE<=STATE3; END IF;
  WHEN STATE3=>
     IF Q1="000" THEN LIGHT<='0'; LED1<="000"; sound<='0'; END IF;    
   WHEN STATE2=>
      IF(I1='1' AND B='1')THEN 
        LED2<="001"; B<='0'; SEL<="001"; SOUND<='1';
      ELSIF (I2='1' AND B='1') THEN 
        LED2<="010"; B<='0'; SEL<="010"; SOUND<='1';
      ELSIF (I3='1' AND B='1') THEN 
        LED2<="011"; B<='0'; SEL<="011"; SOUND<='1';
      ELSIF (I4='1' AND B='1') THEN 
        LED2<="100"; B<='0'; SEL<="100"; SOUND<='1';
      END IF;
      IF (B='0' AND I1='0') THEN SOUND<='0'; END IF;
       IF (B='0' AND I2='0') THEN SOUND<='0'; END IF;
       IF (B='0' AND I3='0') THEN SOUND<='0'; END IF;
        IF (B='0' AND I4='0') THEN SOUND<='0'; END IF;
END CASE;
END IF; end if; END PROCESS;
PROCESS (RESET, CLK, q1)

  BEGIN
    IF RESET='1' THEN Q1<="100";
    ELSE IF (CLK'EVENT AND CLK='1') THEN
     IF Q1="000" THEN Q1<="000";
     ELSE Q1<=Q1-1;
     END IF;
    END IF; END IF;
END PROCESS;
C<= ( NOT B) or reset;
END zt;



LIBRARY IEEE;                          --计分模块
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY jifen IS
PORT (add1, RESET, sub1: IN STD_LOGIC;
     sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
     mark1, mark2, mark3, mark4: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END jifen;
ARCHITECTURE jf OF jifen IS
SIGNAL  CNT1, CNT2, CNT3, CNT4:STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL  cnt11, cnt22, cnt33, cnt44 STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN 
   PROCESS (add1, sel, reset, cnt1, cnt2, cnt3, cnt4)
   BEGIN
   IF RESET='1' THEN CNT1<="0010"; CNT2<="0010"; CNT3<="0010"; CNT4<="0010";
    ELSE
      if  (add1'event and add1='1') then
      CASE SEL IS
      WHEN "001" => CNT1<=CNT1+1; 
                
      WHEN "010" => CNT2<=CNT2+1;
              
      WHEN "011" =>CNT3<=CNT3+1;
              
      WHEN "100" => CNT4<=CNT4+1;
      WHEN others =>null;
   END CASE;
  END IF; end if;
END PROCESS;
 PROCESS (sub1, sel, reset, cnt11, cnt22, cnt33, cnt44)
   
   BEGIN
   IF RESET='1' THEN CNT11<="0101"; CNT22<="0101"; CNT33<="0101";
CNT44<="0101";
    ELSE
      if (sub1'event and sub1='1') then
      CASE SEL IS
      WHEN "001" =>
                  CNT11<=CNT11-1;  
      WHEN "010" =>
                CNT22<=CNT22-1;  
      WHEN "011" =>
                  CNT33<=CNT33-1;  
      WHEN "100" =>
                 CNT44<=CNT44-1; 
      WHEN others =>null;
   END CASE;
  END IF; end if;
END PROCESS;
mark1<=CNT1+cnt11; mark2<=CNT2+cnt22; mark3<=CNT3+cnt33; mark4<=CNT4+CNT44;
END jf;



LIBRARY IEEE;                        --计时模块
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY jishi IS
PORT (en, clk, clk1, reset: IN STD_LOGIC;
     sound : OUT STD_LOGIC;
     q: OUT STD_LOGIC_VECTOR( 7 DOWNTO 0));
END jishi;
ARCHITECTURE js OF jishi IS
SIGNAL q1:STD_LOGIC_VECTOR ( 7 DOWNTO 0);
BEGIN
PROCESS (RESET, clk, en, q1)
BEGIN
IF reset='1' THEN q1<="00010100"; sound<='0';
ELSE 
IF en='1' THEN
 IF (clk'EVENT AND clk='1') THEN
     IF q1="00000000" THEN q1<="00000000";
     ELSE q1<=q1-1;
     END IF;
    END IF; END IF; END IF;
IF q1="00000000" THEN sound<=clk1;
ELSE sound<='0'; END IF;
q<=q1;
END PROCESS; END js;



LIBRARY IEEE;                        --顶层模块
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY qiangdaqi IS
PORT (k1, k2, k3, k4: IN STD_LOGIC;
     RESET, START, CLKK, clkk1: IN STD_LOGIC;
     ADD, SUB: IN STD_LOGIC;
    mark1, mark2, mark3, mark4: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
     LIGHT, SOUND: OUT STD_LOGIC;
     LED1, LED2: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
     Q : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0));
END qiangdaqi;
ARCHITECTURE qdq OF qiangdaqi IS
  SIGNAL S1:STD_LOGIC_VECTOR (2 DOWNTO 0);
  SIGNAL S2:STD_LOGIC;
COMPONENT jishi IS
    PORT (en, clk, clk1, reset: IN STD_LOGIC;
     q:OUT STD_LOGIC_VECTOR( 7 DOWNTO 0));   
END COMPONENT;
COMPONENT jifen IS
     PORT (add1, RESET, sub1: IN STD_LOGIC;
     sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
     mark1, mark2, mark3, mark4: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT;
COMPONENT zhuangtai IS
  PORT (I1, I2, I3, I4: IN STD_LOGIC;
     RESET, START, CLK: IN STD_LOGIC;
      LIGHT, SOUND: OUT STD_LOGIC;
      LED1, LED2: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
      sel: OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
      C: OUT STD_LOGIC ) ;
END COMPONENT;
   BEGIN
     U1:  zhuangtai PORT MAP (I1=>k1, I2=>k2, I3=>k3, I4=>k4, RESET=>RESET,
START=>START, CLK=>CLKK, LIGHT=>LIGHT, SOUND=>SOUND,
LED1=>LED1, LED2=>LED2, SEL=>S1, C=>S2)
     U2: jifen PORT MAP (add1=>ADD, sub1=>SUB, RESET=>RESET, sel =>S1,
 mark1=>mark1, mark2=>mark2, mark3=>mark3, mark4=>mark4);
  U3: jishi PORT MAP (en=>START, RESET=>S2, q=>q, clk =>CLKK, clk1=>clkk1,
sound =>sound) ;
END QDQ;