second.vhd

来自「读取4*4键盘的键值」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity second is
port(
		clk, reset ,set    : in std_logic;
		enmin              : out std_logic;
		daout              : out std_logic_vector (7 downto 0));
end entity  second ;
architecture fun of  second is
signal count: std_logic_vector( 7 downto 0);
begin
daout <= count;
process ( clk,reset,set ) 
begin 
if (reset='1') then
count <="00000000";
elsif (set='0')then
  if (clk'event and clk='1') then
      if (count(3 downto 0)="1001") then
         if (count <"01100000") then
            if (count="01011001") then
                 enmin <='1'; 
                 count<="00000000"; 				          		           	   		
             else
                 count<=count+7; 
             end if;
           else 
            count<="00000000";
          end if;
       elsif(count <"01100000") then 
             count <= count + 1;
             enmin <='0';
           else
             count<="00000000";
        end if;
  end if;
end if;
end process;
end fun;