代码搜索：Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/324371/13267030

vhd minute1.vhd

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity minute1 is Port( clkm,reset:in std_logic; setm:in std_logic; set: in
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www.eeworm.com/read/324371/13267096

vhd day1.vhd

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity day1 is Port( clkd,set,reset:in std_logic; setd:in std_logic; -
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www.eeworm.com/read/137919/13279440

vhd counter10.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter10 is port(clr,en,clk:in std_logic; carry0:out std_logic; q:out std_logic_vector(3 downto 0));
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www.eeworm.com/read/137919/13279603

vhd count60.vhd

library ieee; use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; entity count60 is port(clk,reset:in std_logic; co:out std_logic; bcd1:out std_logic_vector(3 downto 0)
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www.eeworm.com/read/137361/13326680

vhd test48.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.all; ENTITY test48 IS -- 8位乘法器顶层设计 PORT ( CLKk,hkey : IN STD_LOGIC; START : IN STD_
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www.eeworm.com/read/137358/13326726

vhd counter.vhd

library ieee; --时钟计数模块 use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity counter is port(clk: in std_logic; rst: in std_logic; --计数使能
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www.eeworm.com/read/137126/13345200

vhd source1.vhd

--Source1 地址寻址信号 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity source1 is port(clk:in std_logic; outer:out std_logic_vect
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www.eeworm.com/read/137123/13345209

vhd dis.vhd

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; --库包含 entity DIS is port(din : in std_logic_vector(3 downto 0); -- 显示口令数据 cr_cnt :in std_logic_vector(1
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www.eeworm.com/read/137072/13346426

vhd cnt60.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt60 is port (clk:in std_logic; en,rst:in std_logic; tset,set:in std_logic;----
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www.eeworm.com/read/137072/13346633

vhd cnt_24.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt_24 is port (clk:in std_logic; en,rst,tset,set:in std_logic; -- clk0: in std_logic;
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