count60.vhd

程序用VHDL实现： 利用一秒定时测量频率 并且显示

library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity count60 is
  port(clk,reset:in std_logic;
       co:out std_logic;
       bcd1:out std_logic_vector(3 downto 0);
       bcd10p:out std_logic_vector(2 downto 0));
end count60;

architecture rtl of count60 is
signal bcd1n:std_logic_vector(3 downto 0);
signal bcd10n:std_logic_vector(2 downto 0);
begin 
   bcd1<=bcd1n;
   bcd10p<=bcd10n;
   process(clk,reset)
     begin
      if(reset='1')then
       bcd1n<="0000";
      elsif(clk'event and clk='1')then
         if(bcd1n=9)then
          bcd1n<="0000";
        else
          bcd1n<=bcd1n+1;
        end if;
      end if;
    end process;
process(clk,reset)
 begin
  if(reset='1')then
    bcd10n<="000";
  elsif(clk'event and clk='1')then
   if(bcd1n=9)then
    if(bcd10n=5)then 
     bcd10n<="000";
     co<='1';
    else
     bcd10n<=bcd10n+1;
     co<='0';
    end if;
   end if;
  end if;
end process;
end rtl;