counter.vhd

具有多种功能的电子钟：闹钟

library ieee;  --时钟计数模块
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
  port(clk: in std_logic;
 	   rst: in std_logic;  --计数使能
	   buffertime: in std_logic_vector(23 downto 0 ); --时间加载
	   time: out std_logic_vector(23 downto 0));
  end counter;
architecture con of counter is
 signal regtime :std_logic_vector(23 downto 0);   --当前时间/日期
 begin
  process(clk,rst)
 begin
	if(clk'event and clk='1') then 
      if(rst='1')then
 		regtime<=buffertime;
	elsif(regtime(3 downto 0)="1001")then
           regtime(3 downto 0)<="0000";
          if(regtime(7 downto 4)="0101")then
			regtime(7 downto 4)<="0000";
			if(regtime(11 downto 8)="1001")then
			 regtime(11 downto 8)<="0000";
			 if(regtime(15 downto 12)="0101")then
              regtime(15 downto 12)<="0000";
			if(regtime(23 downto 16)="001001")then
				  regtime(23 downto 16)<="010000";
               elsif(regtime(23 downto 16)="011001")then
                    regtime(23 downto 16)<="100000";
			   elsif(regtime(23 downto 16)="100011")then
                    regtime(23 downto 16)<="000000";
  			    else
				  regtime(23 downto 16)<=regtime(23 downto 16)+1;
             end if;   
               
             else
				  regtime(15 downto 12)<=regtime(15 downto 12)+1;
             end if;   
             else
                  regtime(11 downto 8)<=regtime(11 downto 8)+1;
			 end if;
            	else
				  regtime(7 downto 4)<=regtime(7 downto 4)+1;
			  end if;
            	else 
				  regtime(3 downto 0)<=regtime(3 downto 0)+1;
				
     end if;   
     end if; 
	end process;
time<=regtime;
end con;