test48.vhd

来自「8位相 加乘法器」· VHDL 代码 · 共 48 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY test48 IS                            -- 8位乘法器顶层设计
    PORT ( CLKk,hkey : IN STD_LOGIC;
          START : IN STD_LOGIC;
               A : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               B : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
               mmax : out STD_LOGIC_VECTOR(3 DOWNTO 0);
         ARIEND : OUT STD_LOGIC;
           DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) );
END;
ARCHITECTURE struc OF test48 IS
  SIGNAL count,maxx : STD_LOGIC_VECTOR(3 DOWNTO 0);
  SIGNAL counter : STD_LOGIC_VECTOR(23 DOWNTO 0);
BEGIN
   
--*** END FOR BETTER ***
process(clkk)
	begin
		if(a<"1000000"or b<"10000000")then
			ariend<='1';
		end if;
		if(clkk'event and clkk='1')then
			counter<=counter+'1';
		end if;
end process;
dout<=counter(23 downto 8);
process(hkey)
	begin
		if(hkey'event and hkey='1')then
			maxx<=maxx+'1';
		end if;
end process;
mmax<=maxx;
process(clkk)
begin
	if clkk'event and clkk='1'then
		if(count<maxx)then
			count<=count+'1';
		else
			count<="0000";
		end if;
	end if;
end process;
END struc;