minute1.vhd

来自「VHDL写的数字钟」· VHDL 代码 · 共 42 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity minute1 is
 Port(
	  clkm,reset:in std_logic;
	  setm:in std_logic;
	  set: in  std_logic;
      min: buffer std_logic_vector(7 downto 0);      -- ―分输出端
      enmin:out std_logic
	 );              --―分计时器的进位，用来驱动时计时器
End;
Architecture b of minute1 is
	signal min1,min2:std_logic_vector(7 downto 0); 
Begin

 Process(clkm,reset,setm,set)
	variable m:std_logic_vector(7 downto 0);
  Begin
   If reset='0' then 
		min<="00000000";          -- 对分计时器清0
   elsif set='1' then 
     if rising_edge(setm) then
       if m=59 then 
		   m:="00000000"; 
  	   else 
		   m:=m+1;
	   end if;                              -- 以驱动下一级
     end if;
	 min<=m;
   elsif clkm'event and clkm='1' then
		if min=59 then
			min<="00000000";
			enmin<='1';
		else
			min<=min+1;
			enmin<='0';
		end if;
	end if;
End process;		
End;