topclock.vhd.bak

来自「VHDL写的数字钟」· BAK 代码 · 共 51 行

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity topclock is
 Port(clk,reset,set:in std_logic;
S1,m1,h1:in std_logic_vector(1 downto 0);
D1: in std_logic_vector(1 downto 0);
Alarm:out std_logic;
Sec,min,hour:buffer std_logic_vector(1 downto 0);
Day:out std_logic_vector(1 downto 0));
End;
Architecture one of topclock is
  Component second1                                       -- ――秒元件的例化
Port(clk,reset,set: in std_logic;
           S1: in std_logic_vector(1 downto 0);        
           Sec:buffer std_logic_vector(1 downto 0);
           Ensec:out std_logic);
    End Component;
  Component minute1                                        --――分元件的例化
Port(clk,reset,set: in std_logic;
           m1: in std_logic_vector(1 downto 0);
           min:buffer std_logic_vector(1 downto 0);
           Enmin:out std_logic);
    End Component;
  Component hour1                                         -- ――时元件的例化
Port(clkh,reset,set: in std_logic;
           h1: in std_logic_vector(1 downto 0);
           hour:buffer std_logic_vector(1 downto 0);
           Enhour:out std_logic);
    End Component;
  Component day1                                          -- ――星期元件的例化
Port(clkd,reset,set: in std_logic;
           d1: in std_logic_vector(1 downto 0);
           day:buffer std_logic_vector(1 downto 0));
    End Component;
  Component alarm1                                        -- ――报时元件的例化
Port(reset: in std_logic;
           min: in std_logic_vector(1 downto 0);
           alarm:out std_logic);
   End Component;
signal enm,enh,enda:std_logic;                -- ――秒分、分时、时星期之间的连接信号
signal ena:std_logic_vector(1 downto 0);             --――分与报时之间的连接信号
begin
u1:second1 port map(reset=>reset,set=>set,s1=>s1,sec=>sec,clk=>clk, ensec=>enm);
u2:minute1 port map(reset=>reset,set=>set,m1=>m1,min=>min, clk=>enm,enmin=>enh);
u3:hour1 port map(reset=>reset,set=>set,h1=>h1,hour=>hour, clkh=>enh,enhour=>enda);
u4:day1 port map(reset=>reset,set=>set,d1=>d1,day=>day,clkd=>enda);
u5:alarm1 port map(reset=>reset,min=>min,alarm=>alarm);
end;