cnt_24.vhd

这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以直接下载,已经编译通过!

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt_24 is
  port (clk:in std_logic;
       en,rst,tset,set:in std_logic;
      -- clk0: in std_logic;
      -- cout:out std_logic;
        ql:buffer std_logic_vector(3 downto 0);
        qh: buffer std_logic_vector(3 downto 0) );
end cnt_24;

architecture one of cnt_24 is
  
begin
  process (clk,rst,en)
    variable templ,temph:std_logic_vector(3 downto 0);
    variable temp: integer;
    variable cq:std_logic;
     begin  
     if rst='1' then templ:=(others=>'0');temph:=(others=>'0'); 
      --elsif  en='1' then  
      elsif clk'event and clk='1' then
           
        if en='1' then
          -- temp:=temp+1;
          if temp=3599 then  temp:=0;            
            if (templ="0011" and temph="0010") then 
		     templ:="0000";temph:="0000";
		      elsif templ="1001" then templ:="0000";
			    if temph="0010"  then  temph:="0000";
				   else temph:=temph+1;
				 end if;
				 else templ:=templ+1;
			end if;
		   else temp:=temp+1;
		   end if;	
		 else 
		     --if clk0'event and clk0='1' then
		      if set='1' then
		       if templ="1001" then templ:="0000";
		       else templ:=templ+1 ;
		       end if;	
		      end if;
		      if tset='1' then 
		       if temph="0010" then temph:="0000";
		       else temph:=temph+1 ;
		       end if;	
		      end if;
		  end if;
		end if;	
		
		
		ql<=templ;qh<=temph;
		
		--cout<=templ(1) and templ(0) and temph(1) and en;
		
     end process;  
  end one;