cnt60a.vhd

来自「这是我在学习过程中编的数字钟的原程序,含各种时钟模块,以及计数器,累加器等,可以」· VHDL 代码 · 共 63 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt60a is
  port (clk:in std_logic;
        --clk0:in std_logic;
       en,rst:in std_logic;
         tset,set:in std_logic;----
      -- cout:out std_logic;
        ql:buffer std_logic_vector(3 downto 0);
        qh:buffer std_logic_vector(3 downto 0));
end entity;

architecture one of cnt60a is
  
  
begin
  
p1:  process (clk,en,rst,set,tset)
  variable  templ,temph:std_logic_vector(3 downto 0);
     begin   
        if rst='1' then  ql<=(others=>'0');qh<=(others=>'0');
       -- elsif en='1' then   
          elsif clk'event and clk='1' then 
           if en='1' then                   
             if templ="1001" then templ:="0000";
				      if temph="0101"  then  temph:="0000";
				        if ql="1001" then ql<="0000";
				            if qh="0101" then qh<="0000";
				             else qh<=qh+1;
				            end if;
				        else   ql<=ql+1;
				        end if;
				       else temph:=temph+1;
				       end if;
				  else templ:=templ+1;
				 end if;
		   --end if;
		      else 
		   --if clk'event and clk='1' then
		      if set='1' then
		       if ql="1001" then ql<="0000";
		       else ql<=ql+1 ;
		       end if;
		      end if;
		     if tset='1' then
		       if qh="0101" then qh<="0000";
		       else qh<=qh+1 ;
		       end if;
		      end if;
		--ql<=templ;
		--qh<=temph;
		 
		   end if;
		--ql<=templ;
		--qh<=temph;
		
		end if;	
		
     end process p1;
      
end one;