代码搜索：Logic Analyzer

找到约 10,000 项符合「Logic Analyzer」的源代码

代码结果 10,000
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/453409/7421225

vhd m8.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity m8 is port(reset,clk :in std_logic; q :out std_logic_vector(2 downto 0)); end m8; archit
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www.eeworm.com/read/453409/7421243

vhd xiaosh.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity xiaosh is port(clk,reset,en,stop :in std_logic; able :in std_logic; co
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www.eeworm.com/read/453409/7421305

vhd lichengji1.vhd

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity lichengji1 is port(clk,reset,stop :in std_logic; en :out std_logic; shi_1,ge_0
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www.eeworm.com/read/453089/7427004

vhd myclk.vhd

library ieee; use ieee.std_logic_1164.all; entity myclk is port(clk:in std_logic; ds4,ds5:out std_logic; y:out std_logic_vector(6 downto 0); yy:out std_logic_vector
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www.eeworm.com/read/452301/7442172

vhd initflgs.vhd

-------------------------------------------------------------------------------- -- -- File : initflgs.vhd -- Last Modification: 06/26/2001 -- -- Created In SpDE Version: SpDE 8.22 -- Author : R
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www.eeworm.com/read/452301/7442182

tb pci_tar.tb

-------------------------------------------------------------------------------- -- -- File : pci_tar.tb -- Last Modification: 06/26/2001 -- -- Created In SpDE Version: SpDE 8.22 -- Author : Ric
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www.eeworm.com/read/452301/7442205

tb pci_mast.tb

-------------------------------------------------------------------------------- -- -- File : pci_mast.tb -- Last Modification: 06/26/2001 -- -- Created In SpDE Version: SpDE 8.22 -- Author : Ri
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www.eeworm.com/read/452277/7442819

vhd cdu10.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CDU10 IS PORT( CLK: IN STD_LOGIC; CLR: IN STD_LOGIC; EN: IN STD_LOGIC; CN:
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www.eeworm.com/read/452277/7442906

vhd cdu6.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CDU6 IS PORT( CLK,CLR,EN: IN STD_LOGIC; CN: OUT STD_LOGIC; COUNT6: OU
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www.eeworm.com/read/452277/7442999

vhd cdu10.vhd

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CDU10 IS PORT( CLK: IN STD_LOGIC; CLR: IN STD_LOGIC; EN: IN STD_LOGIC; CN:
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