pci_mast.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

--------------------------------------------------------------------------------
--
-- File : pci_mast.tb
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	This is a PCI master model.
--	Please see "The QL5064 PCI Bus Simulation Environment" for detailed informaiton.
--
-- Hierarchy:
--	The tf_pci_master entity is to be used in pci5(3/4)32_208.tb.
--
-- History:	
--	Date	        Author					Version
--  06/26/01		Richard Yuan			1.0
--		- Header reorganized to conform to coding standard.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pci_pack.all;

--This external master does not drive random bits on upper 32 address/data
-- and upper be's when doing 32 bit accesses.

ENTITY tf_pci_master IS
         GENERIC (RW_BUFF_SIZE_ADDR_BITS : integer := 8);

         PORT (
              pci_clk     : IN    std_logic;
              pci_ad     : INOUT std_logic_vector(63 downto 0);
              pci_cbe     : OUT   std_logic_vector(7 downto 0);
              par     : INOUT std_logic;
              par_64     : INOUT std_logic;
              frame_l     : INOUT std_logic;
              irdy_l     : INOUT std_logic;
              trdy_l     : IN    std_logic;
              stop_l     : IN    std_logic;
              devsel_l     : IN    std_logic;
              idsel     : INOUT std_logic;
              req64_l     : OUT   std_logic;
              ack64_l     : IN    std_logic;
              req_l     : OUT   std_logic;
              gnt_l     : IN    std_logic;
              reset_l     : IN    std_logic;
              start_bit     : IN    std_logic;
              done_bit     : OUT    std_logic;
              master_addr   : IN std_logic_vector(63 downto 0);
              master_command : IN std_logic_vector(3 downto 0);
              master_addr_parity     : IN    std_logic;
              master_data_parity     : IN    std_logic;
              master_dword_count : IN integer;
              master_initial_data_delay : IN integer;
              master_next_data_delay : IN integer;
			  master_bad_parity_phase : in integer;
              master_m64bit : IN std_logic;
              master_quiet : IN std_logic;
              be_array : IN BYTE_ARRAY_TYPE;
              data_array : IN DATA_ARRAY_TYPE;
			  pass : OUT std_logic;
               last_data : OUT std_logic_vector(63 downto 0)
         );
END tf_pci_master;

ARCHITECTURE tf_pci_master_ARC_CORE OF tf_pci_master IS

-- this simulates the clock-to-out timing for 33MHz
CONSTANT OUTPUT_DELAY : time := 11 NS;

----PARAMETER
CONSTANT ZEROS32 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
CONSTANT RW_BUFF_SIZE : integer := 2 ** RW_BUFF_SIZE_ADDR_BITS;

------- SIGNALS that get initialized at beginning
SIGNAL pci_ad_oe   : std_logic := '0';
SIGNAL pci_cbe_oe   : std_logic := '0';
SIGNAL frame_oe   : std_logic := '0';
SIGNAL idsel_oe   : std_logic := '0';
SIGNAL irdy_oe   : std_logic := '0';
SIGNAL req64_oe   : std_logic := '0';
SIGNAL req_reg   : std_logic := '0';

SIGNAL force_32 : std_logic := '0';
SIGNAL disconnect_req64   : std_logic := '0';

SIGNAL fake_a_DAC : std_logic := '0';

-- OUTPUT SIGNALS (TEMPS)
SIGNAL pci_cbe_outtmp   : std_logic_vector(7 downto 0);
SIGNAL req64_l_outtmp   : std_logic;
SIGNAL req_l_outtmp   : std_logic;
-- Wires -> SIGNALs
SIGNAL par64_reg_with_error   : std_logic;
SIGNAL par_reg_with_error : std_logic;
SIGNAL irdy   : std_logic;
SIGNAL devsel   : std_logic;
SIGNAL frame   : std_logic;
SIGNAL trdy   : std_logic;
SIGNAL stop   : std_logic;
SIGNAL local_req64_l   : std_logic;
SIGNAL gnt   : std_logic;
SIGNAL reset   : std_logic;
SIGNAL perr64_injected   : std_logic;
SIGNAL perr_injected   : std_logic;

-- Regs -> SIGNALs
SIGNAL frame_reg   : std_logic;
SIGNAL pci_cbe_reg   : std_logic_vector(7 downto 0);
SIGNAL par64_reg   : std_logic;
----SIGNAL start_address   : std_logic_vector(63 downto 0);
SIGNAL irdy_oe_dly   : std_logic;
SIGNAL par_oe_reg   : std_logic;
SIGNAL par_reg   : std_logic;
SIGNAL idsel_reg   : std_logic;
SIGNAL par64_oe_reg   : std_logic;
SIGNAL irdy_dly   : std_logic;
SIGNAL frame_dly   : std_logic;
SIGNAL irdy_reg   : std_logic;
SIGNAL pci_ad_reg   : std_logic_vector(63 downto 0);
SIGNAL bus_idle_ready_to_start   : std_logic;

-- integers -> INTEGERS
SIGNAL phase_count   : integer;
signal master_bad_parity_phase_dly : integer := 0;

-- TEMP SIGNALs
  
---- PROCEDURES
procedure compare64(addr : IN std_logic_vector(63 downto 0);
                    expected : IN std_logic_vector(63 downto 0);
                    SIGNAL actual : IN std_logic_vector(63 downto 0);
                    be : IN std_logic_vector(7 downto 0);
                    VARIABLE pass_fail : INOUT std_logic;
                    quiet : IN std_logic;
                    VARIABLE last_data : OUT std_logic_vector(63 downto 0)) IS
VARIABLE be_mask : std_logic_vector(63 downto 0);
VARIABLE jptempvar4   : std_logic_vector(7 downto 0);
VARIABLE jptempvar5   : std_logic_vector(7 downto 0);
VARIABLE jptempvar6   : std_logic_vector(7 downto 0);
VARIABLE jptempvar7   : std_logic_vector(7 downto 0);
VARIABLE jptempvar8   : std_logic_vector(7 downto 0);
VARIABLE jptempvar9   : std_logic_vector(7 downto 0);
VARIABLE jptempvar10   : std_logic_vector(7 downto 0);
VARIABLE jptempvar11   : std_logic_vector(7 downto 0);
BEGIN
   IF be(7) = '1' THEN jptempvar4 := "11111111";
    ELSE jptempvar4 := "00000000"; END IF;
   IF be(6) = '1' THEN jptempvar5 := "11111111";
    ELSE jptempvar5 := "00000000"; END IF;
   IF be(5) = '1' THEN jptempvar6 := "11111111";
    ELSE jptempvar6 := "00000000"; END IF;
   IF be(4) = '1' THEN jptempvar7 := "11111111";
    ELSE jptempvar7 := "00000000"; END IF;
   IF be(3) = '1' THEN jptempvar8 := "11111111";
    ELSE jptempvar8 := "00000000"; END IF;
   IF be(2) = '1' THEN jptempvar9 := "11111111";
    ELSE jptempvar9 := "00000000"; END IF;
   IF be(1) = '1' THEN jptempvar10 := "11111111";
    ELSE jptempvar10 := "00000000"; END IF;
   IF be(0) = '1' THEN jptempvar11 := "11111111";
    ELSE jptempvar11 := "00000000"; END IF;
   be_mask(63 downto 0) :=   (  ( jptempvar4 )  & --THIS IS CONCATENATION
                   ( jptempvar5 )  & --THIS IS CONCATENATION
                   ( jptempvar6 )  & --THIS IS CONCATENATION
                   ( jptempvar7 )  & --THIS IS CONCATENATION
                   ( jptempvar8 )  & --THIS IS CONCATENATION
                   ( jptempvar9 )  & --THIS IS CONCATENATION
                   ( jptempvar10 )  & --THIS IS CONCATENATION
                   ( jptempvar11 )  ) ;
------jptempvar12 <=  '1' WHEN 
 ------( expected(63 downto 0) AND  be_mask(63 downto 0) )  /=  (  )  ELSE '0';
   IF (expected(63 downto 0) AND be_mask(63 downto 0)) /= (actual(63 downto 0) AND be_mask(63 downto 0)) THEN
       pass_fail :=  '0';
       IF  (  NOT quiet )  = '1'  THEN
          ASSERT (False)
            REPORT "FAILURE: PCI side quad word data read mismatch at address " &
                    vec2hstr(addr) &
                    "." & LF & "Expected: " &
                    vec2hstr(expected AND be_mask) & LF &
                    "Actual: " &
                    vec2hstr(actual AND be_mask)
            SEVERITY Error;
          -----------error_bit.toggle;
       ELSE 
          ----error_bit.toggle_hidden;
       END IF;
   END IF;
   last_data(63 downto 0) :=  actual(63 downto 0) AND  be_mask(63 downto 0);

end compare64;

procedure compare (addr : IN std_logic_vector(63 downto 0);
                   expected : IN std_logic_vector(31 downto 0);
                   SIGNAL actual : IN std_logic_vector(31 downto 0);
                   be : IN std_logic_vector(3 downto 0);
                   VARIABLE pass_fail : INOUT std_logic;
                   quiet : IN std_logic;
                   VARIABLE last_data : OUT std_logic_vector(63 downto 0)) IS
VARIABLE be_mask : std_logic_vector(31 downto 0);
VARIABLE jptempvar13   : std_logic_vector(7 downto 0);
VARIABLE jptempvar14   : std_logic_vector(7 downto 0);
VARIABLE jptempvar15   : std_logic_vector(7 downto 0);
VARIABLE jptempvar16   : std_logic_vector(7 downto 0);
BEGIN
   IF be(3) = '1' THEN jptempvar13 := "11111111";
    ELSE jptempvar13 := "00000000"; END IF;
   IF be(2) = '1' THEN jptempvar14 := "11111111";
    ELSE jptempvar14 := "00000000"; END IF;
   IF be(1) = '1' THEN jptempvar15 := "11111111";
    ELSE jptempvar15 := "00000000"; END IF;
   IF be(0) = '1' THEN jptempvar16 := "11111111";
    ELSE jptempvar16 := "00000000"; END IF;
   be_mask(31 downto 0) :=   (  ( jptempvar13 )  & --THIS IS CONCATENATION
               ( jptempvar14 )  & --THIS IS CONCATENATION
               ( jptempvar15 )  & --THIS IS CONCATENATION
               ( jptempvar16 )  ) ;
   ----jptempvar17 := '1' WHEN 
        ----(expected(31 downto 0) AND  be_mask(31 downto 0) )  /=  (  )  ELSE '0';
   IF (expected(31 downto 0) AND be_mask(31 downto 0)) /= (actual(31 downto 0) AND be_mask(31 downto 0)) THEN
       pass_fail :=  '0';
       IF  (NOT quiet) = '1' THEN
          ASSERT (False)
            REPORT "FAILURE: PCI side double word data read mismatch at address " &
                    vec2hstr(addr) &
                    "." & LF & "Expected: " &
                    vec2hstr(expected AND be_mask) & LF &
                    "Actual: " &
                    vec2hstr(actual AND be_mask)
            SEVERITY Error;
          -----------error_bit.toggle;
       ELSE 
          ----error_bit.toggle_hidden;
       END IF;
   END IF;
---   jptempvar18 <=  '1' WHEN 
---      ( be_mask(63 downto 0) )  /=  0  ELSE '0';
   IF be_mask(31 downto 0) /= ZEROS32 THEN
      IF  ( addr(2) )  = '1'  THEN
          last_data(63 downto 0) := ( (actual(31 downto 0) AND  be_mask(31 downto 0)) & --THIS IS CONCATENATION
                        "00000000000000000000000000000000" ) ;
      ELSE
          last_data(63 downto 0) := ( "00000000000000000000000000000000" & --THIS IS CONCATENATION
                     (actual(31 downto 0) AND  be_mask(31 downto 0)) ) ;
      END IF;
   END IF;
end compare;

---------- PROCEDURE (MAIN)
PROCEDURE target_access_one_frame(VARIABLE address : IN std_logic_vector(63 downto 0);
                                  command : IN std_logic_vector(3 downto 0);
                                  addr_parity : IN std_logic;
                                  data_parity : IN std_logic;
                                  VARIABLE burst_count : IN integer;
                                  initial_data_delay : IN integer;
                                  next_data_delay : IN integer;
                                  m64bit_in : IN std_logic;
                                  initial_array_position : IN integer;
                                  VARIABLE pass_fail : INOUT std_logic;
                                  quiet : IN std_logic;
                                  last_data : INOUT std_logic_vector(63 downto 0);
                                  hold_req : IN std_logic;
                                  SIGNAL req_reg : INOUT std_logic;
                                  SIGNAL irdy_reg : INOUT std_logic;
                                  SIGNAL frame_oe : OUT std_logic;
                                  SIGNAL frame_reg : INOUT std_logic;
                                  SIGNAL idsel_oe : OUT std_logic;
                                  SIGNAL pci_ad_oe : OUT std_logic;
                                  SIGNAL pci_cbe_oe : OUT std_logic;
                                  SIGNAL pci_ad_reg : OUT std_logic_vector(63 downto 0);
                                  SIGNAL pci_cbe_reg : OUT std_logic_vector(7 downto 0);
                                  SIGNAL idsel_reg : OUT std_logic;