pci_tar.tb

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

--------------------------------------------------------------------------------
--
-- File : pci_tar.tb
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	This is a PCI target model.
--	Please see "The QL5064 PCI Bus Simulation Environment" for detailed informaiton.
--
-- Hierarchy:
--	The pci_tar entity is to be used in pci5(3/4)32_208.tb.
--
-- History:	
--	Date	        Author					Version
--  06/26/01		Richard Yuan			1.0
--		- Header reorganized to conform to coding standard.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;
use work.pci_pack.Unary_XOR;
ENTITY pci_parity_check IS
         PORT (
              ad_p     : IN    std_logic_vector(63 downto 0);
              c_be_n_p     : IN    std_logic_vector(7 downto 0);
              parity32     : OUT   std_logic;
              parity64     : OUT   std_logic
         );
END pci_parity_check;

ARCHITECTURE pci_parity_check_ARC_CORE OF pci_parity_check IS
BEGIN
--Beginning of actual code
  parity32 <= (Unary_XOR(ad_p(31 downto 0))) XOR (Unary_XOR(c_be_n_p(3 downto 0))) ;
  parity64 <= (Unary_XOR(ad_p(63 downto 32))) XOR (Unary_XOR(c_be_n_p(7 downto 4))) ;
END pci_parity_check_ARC_CORE;



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY pci_tar IS

		 GENERIC (
			  MEM_SIZE : integer := 4096;
              BUS_SIZE   : integer := 32
			  );

         PORT (
              clk     : IN    std_logic;
              pci_ad     : INOUT std_logic_vector(63 downto 0);
              c_be_n     : IN    std_logic_vector(7 downto 0);
              par     : INOUT std_logic;
              par64     : INOUT std_logic;
              frame_n     : IN    std_logic;
              irdy_n     : IN    std_logic;
              trdy_n     : INOUT std_logic;
              devsel_n     : INOUT std_logic;
              req64_n     : IN    std_logic;
              ack64_n     : INOUT std_logic;
              rst_n     : IN    std_logic;
              stop_n     : INOUT std_logic;
              perr_n     : INOUT std_logic;
              RANDOM_VAL : IN integer := 0;
              DEVICE_SPEED   : IN integer := 1;
              BASE_ADDRESS   : IN std_logic_vector(63 downto 0) := (others => '0');
              STOP_COUNT   : IN integer := 5;
              STOP_ENABLE   : IN std_logic := '1';
              WAITSTATES_ENABLE   : IN std_logic := '0';
              VARIABLE_WAITS   : IN std_logic := '0';
              MAX_WAITS   : IN integer := 16;
              MIN_WAITS   : IN integer := 0;
              INITIAL_WAITS   : IN integer := 2;
              SUBSEQUENT_WAITS   : IN integer := 1;
              STOP_WAITS   : IN integer := 2;
              RETRY_COUNT   : IN integer := 10;
              ENABLE_RETRY_COUNT   : IN std_logic := '0';
              WRONG_PAR   : IN std_logic := '0';
              WRONG_PAR64   : IN std_logic := '0';
              PERR_ASSERT   : IN std_logic := '0';
              TARGET_ABORT   : IN std_logic := '0'
         );
END pci_tar;
       ---DEVICE_SPEED---- should be 0-3 range --default: Medium speed device
       ---BASE_ADDRESS--Base address for this device
       ---BUS_SIZE --32 or 64 bit bus
       ---STOP_COUNT--Number of data phases before asserting stop
       ---STOP_ENABLE--Enables ability to assert stop
       ---WAITSTATES_ENABLE --Enable insertion of stop states
       ---VARIABLE_WAITS --Enable variable wait lengths (INITIAL_WAITS and SUBSEQUENT_WAITS are ignored)
       ---MAX_WAITS--Max # of wait states inserted in variable waits mode
       ---MIN_WAITS--Min # of wait states inserted in variable waits mode 
       ---INITIAL_WAITS--# of waits to insert before first trdy
       ---SUBSEQUENT_WAITS---# of waits to insert before subsequent trdy's
       ---STOP_WAITS--# of waits to pause before asserting stop (after STOP_COUNT data phases)
       ---RETRY_COUNT--# of times to assert stop before setting STOP_ENABLE to 0
       ---ENABLE_RETRY_COUNT--Disable Retry Count By Default

ARCHITECTURE pci_tar_ARC_CORE OF pci_tar IS

-- this simulates the clock-to-out timing for 33MHz
CONSTANT OUTPUT_DELAY : time := 11 NS;

-- OUTPUT SIGNALS (TEMPS)
CONSTANT idle : std_logic_vector(7 downto 0) := "00000001";
CONSTANT read_turnaround : std_logic_vector(7 downto 0) := "00000010";
CONSTANT s_data : std_logic_vector(7 downto 0) := "00000100";
CONSTANT w_data : std_logic_vector(7 downto 0) := "00001000";
CONSTANT wait_cycle : std_logic_vector(7 downto 0) := "00100000";
CONSTANT dualaddress_cycle : std_logic_vector(7 downto 0) := "01000000";
CONSTANT aborting : std_logic_vector(7 downto 0) := "10000000";

--------SETTINGS TO CHANGE THE CHARACTERISTICS OF THE TARGET
SIGNAL retry_count_counter : integer;
SIGNAL stop_enable_used : std_logic;


--------SIGNALS THAT ARE INITIALIZED
SIGNAL devsel_activate   : std_logic := '0';
SIGNAL devsel_ok   : std_logic := '0';
SIGNAL Assert_Target_Abort   : std_logic := '0';


-- Wires -> SIGNALs
SIGNAL req64   : std_logic;
SIGNAL stop_en   : std_logic;
SIGNAL irdy   : std_logic;
SIGNAL memcheck   : std_logic_vector(63 downto 0);
SIGNAL write_trdy_en   : std_logic;
SIGNAL trdy_reg   : std_logic;
SIGNAL stop_reg   : std_logic;
SIGNAL devsel   : std_logic;
SIGNAL frame   : std_logic;
SIGNAL ADDRESS_64   : std_logic;
SIGNAL dataout_reg   : std_logic_vector(63 downto 0);
SIGNAL match64   : std_logic;
SIGNAL trdyoe   : std_logic;
SIGNAL rst   : std_logic;
SIGNAL ack64   : std_logic;
SIGNAL parity64_out   : std_logic;
SIGNAL trdy   : std_logic;
SIGNAL stop   : std_logic;
SIGNAL match   : std_logic;
SIGNAL target_selected   : std_logic;
SIGNAL parity32_out   : std_logic;
SIGNAL adoe   : std_logic;
SIGNAL old_devsel   : std_logic;
SIGNAL increment   : integer;
SIGNAL new_devsel   : std_logic;
SIGNAL ack64_oe   : std_logic;

-- Regs -> SIGNALs
TYPE MEMORY_ARRAY_TYPE is array (0 to MEM_SIZE-1) of std_logic_vector(7 downto 0);
SIGNAL MyMemory : MEMORY_ARRAY_TYPE;
SIGNAL parity_en   : std_logic;
SIGNAL parity64_en   : std_logic;
SIGNAL count_stop   : std_logic;
SIGNAL StopWaits   : integer;
SIGNAL lower_addr   : std_logic_vector(31 downto 0);
SIGNAL target   : std_logic_vector(7 downto 0);
SIGNAL WaitStates   : integer;
SIGNAL perr_en   : std_logic;
SIGNAL stophold   : std_logic;
SIGNAL req64_transaction   : std_logic;
SIGNAL parity32_out_d   : std_logic;
SIGNAL c_be_n_d   : std_logic_vector(7 downto 0);
SIGNAL pci_ad_d   : std_logic_vector(63 downto 0);
SIGNAL stoplatch   : std_logic;
SIGNAL mem_addr   : std_logic_vector(63 downto 0) := (others => '0');
SIGNAL addr_diff   : std_logic_vector(63 downto 0) := (others => '0');
SIGNAL curr_addr   : integer := 0;
SIGNAL check_addr   : integer := 0;
SIGNAL parity64_out_d   : std_logic;
SIGNAL trdylatch   : std_logic;
SIGNAL perr_out   : std_logic;

-- integers -> INTEGERS
SIGNAL data_count   : integer := 0;

-- TEMP SIGNALs
SIGNAL jptempvar0   : std_logic;
SIGNAL jptempvar1   : std_logic;
SIGNAL jptempvar2   : std_logic;
SIGNAL jptempvar3   : std_logic;
SIGNAL jptempvar4   : std_logic;
SIGNAL jptempvar5   : std_logic;
SIGNAL jptempvar6   : std_logic;
SIGNAL jptempvar7   : std_logic;
SIGNAL jptempvar8   : std_logic;
SIGNAL jptempvar9   : std_logic;
SIGNAL jptempvar10   : std_logic;
SIGNAL jptempvar11   : std_logic;
SIGNAL jptempvar12   : std_logic;
SIGNAL jptempvar13   : std_logic;
SIGNAL jptempvar14   : std_logic;
SIGNAL jptempvar15   : std_logic;
SIGNAL jptempvar16   : std_logic;
SIGNAL jptempvar17   : std_logic;
SIGNAL jptempvar18   : std_logic;
SIGNAL jptempvar19   : std_logic;
SIGNAL jptempvar20   : std_logic;
SIGNAL jptempvar21   : std_logic;
SIGNAL jptempvar22   : std_logic;
SIGNAL jptempvar23   : std_logic;
SIGNAL jptempvar24   : std_logic;
SIGNAL jptempvar25   : std_logic;
SIGNAL jptempvar26   : integer;
SIGNAL jptempvar27   : std_logic_vector(7 downto 0);
SIGNAL jptempvar28   : std_logic;
SIGNAL jptempvar29   : std_logic_vector(7 downto 0);
SIGNAL jptempvar30   : std_logic;
SIGNAL jptempvar31   : std_logic_vector(7 downto 0);
SIGNAL jptempvar32   : std_logic;
SIGNAL jptempvar33   : std_logic_vector(7 downto 0);
SIGNAL jptempvar34   : std_logic;
SIGNAL jptempvar35   : std_logic_vector(7 downto 0);
SIGNAL jptempvar36   : std_logic_vector(7 downto 0);
SIGNAL jptempvar37   : std_logic_vector(7 downto 0);
SIGNAL jptempvar38   : std_logic_vector(7 downto 0);
SIGNAL jptempvar39   : std_logic;
SIGNAL jptempvar40   : std_logic;
SIGNAL jptempvar41   : std_logic;
SIGNAL jptempvar42   : std_logic;
SIGNAL jptempvar43   : std_logic;
SIGNAL jptempvar44   : std_logic;
SIGNAL jptempvar45   : std_logic;
SIGNAL jptempvar46   : std_logic;
SIGNAL jptempvar47   : std_logic;
SIGNAL jptempvar48   : integer;
SIGNAL jptempvar49   : std_logic;
SIGNAL jptempvar50   : std_logic;
SIGNAL jptempvar51   : integer;
SIGNAL jptempvar52   : std_logic;
SIGNAL jptempvar53   : integer;
SIGNAL jptempvar54   : std_logic;
SIGNAL jptempvar55   : integer;
SIGNAL jptempvar56   : std_logic;
SIGNAL jptempvar57   : std_logic;
SIGNAL jptempvar58   : std_logic;
SIGNAL jptempvar59   : std_logic;
SIGNAL jptempvar60   : std_logic;
SIGNAL jptempvar61   : std_logic;
SIGNAL jptempvar62   : std_logic;
SIGNAL jptempvar63   : std_logic;
SIGNAL jptempvar64   : std_logic;

COMPONENT pci_parity_check
         PORT (
              ad_p     : IN    std_logic_vector(63 downto 0);
              c_be_n_p     : IN    std_logic_vector(7 downto 0);
              parity32     : OUT   std_logic;
              parity64     : OUT   std_logic
         );
END COMPONENT;



BEGIN
-- The Assigns for the Output Vars

-- The Assigns for the temp Vars
jptempvar0 <=  '1' WHEN 
 std_logic_vector( unsigned(BASE_ADDRESS(63 downto 0)) + to_unsigned(MEM_SIZE, 32) )  >  (  "100000000000000000000000000000000" )  ELSE '0';
jptempvar1 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "1101" )  ELSE '0';
jptempvar2 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "1101" )  ELSE '0';
jptempvar3 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "0110" )  ELSE '0';
jptempvar4 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "0111" )  ELSE '0';
jptempvar5 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "1100" )  ELSE '0';
jptempvar6 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "1110" )  ELSE '0';
jptempvar7 <=  '1' WHEN 
 ( c_be_n(3 downto 0) )  =  (  "1111" )  ELSE '0';