pci_tar.tb

来自「VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用」· TB 代码 · 共 854 行 · 第 1/3 页

  pci_ad(31 downto 24) <=   ( jptempvar35 ) after OUTPUT_DELAY WHEN  ( adoe )  = '1'  ELSE "ZZZZZZZZ" after OUTPUT_DELAY;
  pci_ad(23 downto 16) <=   ( jptempvar36 ) after OUTPUT_DELAY WHEN  ( adoe )  = '1'  ELSE "ZZZZZZZZ" after OUTPUT_DELAY;
  pci_ad(15 downto  8) <=   ( jptempvar37 ) after OUTPUT_DELAY WHEN  ( adoe )  = '1'  ELSE "ZZZZZZZZ" after OUTPUT_DELAY;
  pci_ad( 7 downto  0) <=   ( jptempvar38 ) after OUTPUT_DELAY WHEN  ( adoe )  = '1'  ELSE "ZZZZZZZZ" after OUTPUT_DELAY;
  adoe <= jptempvar39;
  old_devsel <=  '1' WHEN  (  ( adoe OR  write_trdy_en )  )  = '1'  ELSE  '0';
  devsel_n <= new_devsel after OUTPUT_DELAY;
  write_trdy_en <= jptempvar40;
  target_selected <= jptempvar41;
 

set_devsel: PROCESS
BEGIN
 wait on clk until clk = '1'; --- to do always @(posedge clk)
   IF ((match OR match64) = '1') THEN
      
----FOR devsel_delay=0;  devsel_delay < DEVICE_SPEED; devsel_delay = devsel_delay + 1
      FOR devsel_delay IN 0 to DEVICE_SPEED-1 LOOP
          wait until rising_edge(clk);
      END LOOP;
      IF  ( TARGET_ABORT )  = '1'  THEN
          devsel_ok <=  '1';
          devsel_activate <=  '1';
          IF  ( jptempvar42 )  = '1'  THEN
              wait until rising_edge(clk);
          END IF;
        wait until rising_edge(clk);
        wait until rising_edge(clk);
          devsel_activate <=  '0';
          devsel_ok <=  '0';
          Assert_Target_Abort <=  '1';
        wait until rising_edge(clk);
          WHILE frame = '1' LOOP
            wait until rising_edge(clk);
          END LOOP;
          Assert_Target_Abort <=  '0';
      ELSE
          devsel_ok <=  '1';
          devsel_activate <=  '1';
          IF  ( jptempvar43 )  = '1'  THEN
            wait until rising_edge(clk);
          END IF;
        wait until rising_edge(clk);
          devsel_activate <=  '0';
        wait until rising_edge(clk);
          WHILE old_devsel = '1' LOOP
            wait until rising_edge(clk);
          END LOOP;
          devsel_ok <=  '0';
      END IF;
   END IF;

END PROCESS;

new_devsel <=  '0' WHEN  (  (  (  ( old_devsel OR  devsel_activate )  )  AND  (  devsel_ok AND  target_selected )  )  )  = '1'  ELSE  'Z';
  trdy_n <=   (  NOT trdy_reg ) after OUTPUT_DELAY WHEN  ( trdyoe )  = '1'  ELSE  'Z' after OUTPUT_DELAY;
  trdy_reg <=  trdylatch WHEN  ( stoplatch )  = '1'  ELSE   (  (  ( adoe OR  write_trdy_en )  )  AND  (  (  (  NOT  ( jptempvar44 )  )  )  AND  (   (  (  ( jptempvar45 )  OR  (  NOT WAITSTATES_ENABLE )  )  )  AND  (   ( devsel_ok )  AND   (  NOT TARGET_ABORT )  )  )  )  ) ;
  trdyoe <= adoe OR  write_trdy_en;
 

--ALWAYS: posedge clk or posedge rst) begin if (rst) begin       trdylatch <= 1'b0
trdy_stop_latch: PROCESS ( clk, rst)
BEGIN
 IF  ( rst )  = '1'  THEN
       trdylatch <=  '0';
        stoplatch <=  '0';
 --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
IF  (  (  (  NOT stop_n )  )  AND  (   (  NOT trdy_n )  AND   (  NOT irdy_n )  )  )  = '1'  THEN
         trdylatch <=  '0';
          stoplatch <=  '1';
  ELSE stoplatch <=  stop;
          trdylatch <=  trdy_reg;
  END IF;
 END IF;
 END PROCESS;



--ALWAYS: posedge clk or posedge rst) begin if (rst) begin       WaitStates <= 0
waits: PROCESS ( clk, rst)
BEGIN
 IF  ( rst )  = '1'  THEN
       WaitStates <=  0;
        StopWaits <=  0;
 --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
  IF  (  ( match64 AND   ( jptempvar46 )  )  OR   ( match AND   ( jptempvar47 )  )  )  = '1'  THEN
         WaitStates <=  jptempvar48;
          StopWaits <=  STOP_WAITS;
  ELSIF  (  (  ( jptempvar49 )  )  AND  (  (  NOT  ( jptempvar50 )  )  AND  irdy )  )  = '1'  THEN
         WaitStates <=  jptempvar51;
          StopWaits <=  STOP_WAITS;
  ELSIF  (  NOT  ( jptempvar52 )  )  = '1'  THEN
         WaitStates <=  jptempvar53;
          StopWaits <=  jptempvar55;
  ELSE
	WaitStates <=  0;
	StopWaits <=  0;
  END IF;
  END IF;
 END PROCESS;

set_MyMemory: PROCESS (clk, rst)
	VARIABLE temp_vec : std_logic_vector(31 downto 0);
	VARIABLE init : integer;
BEGIN
 IF falling_edge(rst) THEN
    FOR init IN 0 to MEM_SIZE-1 LOOP
		temp_vec := std_logic_vector(to_unsigned(init,32));
		MyMemory(init) <=  temp_vec(7 downto 0);
    END LOOP;
 ELSIF rising_edge(clk) THEN
    IF  (  ( irdy )  AND  (  trdy_reg AND  write_trdy_en )  )  = '1'  THEN
       IF  (  NOT c_be_n(0) )  = '1'  THEN
          MyMemory(curr_addr) <=  pci_ad(7 downto 0);
       END IF;
       IF  (  NOT c_be_n(1) )  = '1'  THEN
          MyMemory(curr_addr+1) <=  pci_ad(15 downto 8);
       END IF;
       IF  (  NOT c_be_n(2) )  = '1'  THEN
          MyMemory(curr_addr+2) <=  pci_ad(23 downto 16);
       END IF;
       IF  (  NOT c_be_n(3) )  = '1'  THEN
          MyMemory(curr_addr+3) <=  pci_ad(31 downto 24);
       END IF;
       IF  (  ( jptempvar57 )  AND  ack64 )  = '1'  THEN
          IF  (  NOT c_be_n(4) )  = '1'  THEN
             MyMemory(curr_addr+4) <=  pci_ad(39 downto 32);
          END IF;
          IF  (  NOT c_be_n(5) )  = '1'  THEN
             MyMemory(curr_addr+5) <=  pci_ad(47 downto 40);
          END IF;
          IF  (  NOT c_be_n(6) )  = '1'  THEN
             MyMemory(curr_addr+6) <=  pci_ad(55 downto 48);
          END IF;
          IF  (  NOT c_be_n(7) )  = '1'  THEN
             MyMemory(curr_addr+7) <=  pci_ad(63 downto 56);
          END IF;
       END IF;
    END IF;
 END IF;
END PROCESS;



--ALWAYS: posedge clk or posedge rst) begin if (rst)     data_count <= 0
set_data_count: PROCESS ( clk, rst)
BEGIN
 IF  ( rst )  = '1'  THEN
     data_count <=  0;
 --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
  IF  ( irdy AND  trdy_reg )  = '1'  THEN
       data_count <=  data_count +  1;
  ELSIF  ( jptempvar58 )  = '1'  THEN
       data_count <=  0;
  END IF;
  END IF;
 END PROCESS;

stop_n <=   NOT stop_reg after OUTPUT_DELAY WHEN  ( stop_en )  = '1'  ELSE  'Z' after OUTPUT_DELAY;
  stop_en <=  ( adoe OR  write_trdy_en )  OR  Assert_Target_Abort;
 

--ALWAYS: posedge clk or posedge rst) begin if(rst) begin         stophold <= 1'b0
set_stophold: PROCESS ( clk, rst)
BEGIN
 IF  ( rst )  = '1'  THEN
         stophold <=  '0';
 --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
stophold <=  stop_reg;
  END IF;
 END PROCESS;

stop_reg <= ( (stop_enable_used AND jptempvar59 AND jptempvar60 AND stop_en AND devsel) OR
              (stop_enable_used AND trdy_reg AND jptempvar61 AND jptempvar62) OR
              (stophold AND devsel) OR
              Assert_Target_Abort);
 

--ALWAYS: posedge clk or posedge rst) begin if(rst) begin       count_stop <= 1
retry_stop_count: PROCESS ( clk, rst)
BEGIN
 IF  ( rst )  = '1'  THEN
       count_stop <=  '1';
	   retry_count_counter <= RETRY_COUNT;
	   stop_enable_used <= STOP_ENABLE;
 --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
IF  ( stop_reg AND  count_stop )  = '1'  THEN
 IF  ( jptempvar63 )  = '1'  THEN
               count_stop <= '0';
  ELSE retry_count_counter <=  retry_count_counter -  1;
                  count_stop <=  '0';
  END IF;
 ELSIF  (  NOT stop_reg )  = '1'  THEN
             count_stop <=  '1';
 IF  (  ( jptempvar64 )  AND   ( ENABLE_RETRY_COUNT )  )  = '1'  THEN
                 stop_enable_used <=  '0';
  END IF;
 END IF;
 END IF;
 END PROCESS;


--MODULE (COMPONENT) INSTANCIATION
my_pci_parity_check: pci_parity_check
      port map (
        ad_p=>pci_ad_d(63 downto 0) , 
        c_be_n_p=>c_be_n_d(7 downto 0) , 
        parity32=>parity32_out , 
        parity64=>parity64_out ) ;
 

--ALWAYS: posedge clk or posedge rst) begin if(rst) begin         c_be_n_d[7JPDOWNTO0] <= 8'h0
set_parity: PROCESS ( clk, rst)
BEGIN
 IF  ( rst )  = '1'  THEN
         c_be_n_d(7 downto 0) <=  "00000000";
          pci_ad_d(63 downto 0) <=  "0000000000000000000000000000000000000000000000000000000000000000";
          parity_en <=  '0';
          parity64_en <= '0';
   parity32_out_d <=  '0';
   parity64_out_d <=  '0';
 --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
c_be_n_d(7 downto 0) <=  c_be_n(7 downto 0);
          pci_ad_d(63 downto 0) <=  pci_ad(63 downto 0);
   parity_en <=  adoe;
   parity64_en <= adoe AND (NOT ack64_n);
   parity32_out_d <=  parity32_out;
   parity64_out_d <=  parity64_out;
  END IF;
 END PROCESS;

par <=  parity32_out XOR  WRONG_PAR after OUTPUT_DELAY WHEN  ( parity_en )  = '1'  ELSE  'Z' after OUTPUT_DELAY;
  par64 <=  parity64_out XOR  WRONG_PAR64 after OUTPUT_DELAY WHEN  ( parity64_en )  = '1'  ELSE  'Z' after OUTPUT_DELAY;

report_parity: PROCESS (clk)
BEGIN
   IF rising_edge(clk) THEN
      IF (parity_en = '1') THEN
         ASSERT (NOT (parity32_out = 'X'))
            REPORT "ERROR: parity output from ext. target is X"
            SEVERITY ERROR;
      END IF;
      IF (parity64_en = '1') THEN
         ASSERT (NOT (parity64_out = 'X'))
            REPORT "ERROR: parity 64 output from ext. target is X"
            SEVERITY ERROR;
      END IF;
   END IF;
END PROCESS;
 

--ALWAYS: posedge clk or posedge rst) begin if (rst) begin          perr_out <= 1'b0
set_perr: PROCESS
BEGIN

 wait on rst, clk until (rst = '1' OR clk = '1');
 IF  ( rst )  = '1'  THEN
          perr_out <=  '0';
          perr_en <=  '0';
 --ADDED IF BELOW
 ELSIF rising_edge(clk) THEN
   IF  (  ( irdy )  AND  (  trdy_reg AND  write_trdy_en )  )  = '1'  THEN
      wait until rising_edge(clk);
              perr_en <=  '1';
              perr_out <=  '1';
      wait until rising_edge(clk);
              perr_en <=  '0';
              perr_out <=  '0';
  END IF;
 END IF;

END PROCESS;

perr_n <= (NOT perr_out) after OUTPUT_DELAY WHEN (perr_en AND PERR_ASSERT) = '1' ELSE 'Z' after OUTPUT_DELAY;

END pci_tar_ARC_CORE;