initflgs.vhd

VHDLVERILOG语言实现的CARDBUS的IP源码,已经实现现场应用

--------------------------------------------------------------------------------
--
-- File : initflgs.vhd
-- Last Modification: 06/26/2001
--
-- Created In SpDE Version: SpDE 8.22
-- Author :	Richard Yuan, QuickLogic Corporation
-- Copyright (C) 2001, Licensed customers of QuickLogic may copy and modify
-- this file for use in designing with QuickLogic devices only.
--	
-- Description :
--	This block writes two elements to FIFO immediately after reset, which are
--	used to set the partial empty/full flags on the IDT FIFOs.
--
-- Hierarchy:
--	This file represents the initflgs block in pci5(3/4)32_208.sch.
--
-- History:	
--	Date	        Author					Version
--  06/26/01		Richard Yuan			1.0
--		- Header reorganized to conform to coding standard.
--
--------------------------------------------------------------------------------


library ieee;
use ieee.std_logic_1164.all;

entity initflgs is port
	(
	clk, clr, pushin: in std_logic;
	push: out std_logic;
	datain: in std_logic_vector(31 downto 0);
	dataout: out std_logic_vector(31 downto 0)
	);
end initflgs;

architecture behavior of initflgs is

signal pushinit: std_logic;
signal selector: std_logic;
constant EIGHT_16BITS: std_logic_vector (15 downto 0) := "0000000000001000";

begin
	push <= pushin or pushinit;

	process (clk, clr)
	begin
		if clr = '1' then pushinit <= '0';
		elsif clk'event and clk = '1' then
			if selector = '0' then pushinit <= '1';
			else pushinit <= '0';
			end if;
		end if;
	end process;
		
	process (clk, clr)
	begin
		if clr = '1' then selector <= '0';
		elsif clk'event and clk = '1'	then
			if pushinit = '1' then selector <= '1'; end if;
		end if;
	end process;

	with pushinit select
	dataout <= datain 					   when '0',
			   EIGHT_16BITS & EIGHT_16BITS when '1',
			   (others => 'X')             when others;

end behavior;