myclk.vhd

两位独立数码管100进制计数器

library ieee;
use ieee.std_logic_1164.all;
entity myclk is
 port(clk:in std_logic;
        ds4,ds5:out std_logic;
           y:out std_logic_vector(6 downto 0);
          yy:out std_logic_vector(6 downto 0));
end myclk;
architecture bhv of myclk is
  signal b:integer range 0 to 9;
  signal c:integer range 0 to 9; 
begin
   t1:process(clk)
	   variable a:integer range 0 to 200;
      begin 
          ds4<='0';
          ds5<='0';       
       if clk'event and clk='1' then
         if a<200 then
           a:=a+1;
         else 
           a:=0;
            b<=b+1;
           if b>9  then
             b<=0;
              c<=c+1;
                 if c=9 then
                     c<=0;
                  end if;                        
           end if;
         end if;
       end if;
   end process;
t2:process(b)
   begin
     if b=0 then 
         y<="0111111";
        elsif b=1 then
       y<="0000110";
       elsif b=2 then
       y<="1011011";
     elsif b=3 then
       y<="1001111";
     elsif b=4 then
       y<="1100110";
     elsif b=5 then
       y<="1101101";
     elsif b=6 then
       y<="1111101";
     elsif b=7 then
       y<="0000111";
     elsif b=8 then
       y<="1111111";
     elsif b=9 then
       y<="1101111";
    end if;
end process;
t3:process(c)
   begin
            if c=0 then
                     yy<="0111111";
              elsif c=1 then
                     yy<="0000110";
              elsif c=2 then
                     yy<="1011011";
              elsif c=3 then
                     yy<="1001111";
              elsif c=4 then
                     yy<="1100110"; 
              elsif c=5 then
                     yy<="1101101";
              elsif c=6 then
                    yy<="1111101";
              elsif c=7 then
                    yy<="0000111";
              elsif c=8 then
                    yy<="1111111";
              elsif c=9 then
                    yy<="1101111";
           end if;            
end process;
end bhv;