lichengji1.vhd

来自「出租车的计费系统」· VHDL 代码 · 共 42 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lichengji1 is
  port(clk,reset,stop    :in std_logic;
       en             :out std_logic;
       shi_1,ge_0      :out std_logic_vector(3 downto 0));
end lichengji1;
architecture cnt_100_x of lichengji1 is
     signal shi,ge:std_logic_vector(3 downto 0);
begin
    process(reset,clk)
    begin
        if(reset='1' ) then
          shi<="0000";ge<="0000";
          else if(clk'event and clk='1') then
                  if(ge=9) then ge<="0000";
                     if (shi=9) then shi<="0000";
                       else shi<=shi+1;
                     end if;
                  else ge<=ge+1;
              
                  end if;
              if(ge=3) then
                  en<='1';
              end if;
              if(stop='1') then
                shi<=shi;
                ge<=ge;
              end if;
              end if;
      if(shi=9 and ge=9) then
         ge_0<="0000";
         shi_1<="0000"; 
      else     
       shi_1<=shi;
       ge_0<=ge;
       end if;  
      end if;
end process;
end cnt_100_x;