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61_logic.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package logic_pack is
function resolve(s : std_ulogic_vector) return std_ulogic;
SUBTYPE logic is resolve std_ulogic;
TYPE logic_vector IS ARRAY
block_logic.m
function expression = block_logic(block,sfiptype)
% Find the logical expression at a block output
%
% Syntax:
% "expression = block_logic(block,sfiptype)"
%
% Description:
% "block_logic
frame_logic.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: sdmy
// Engineer: freedom
//
// Create Date: 14:41:02 12/23/2007
// Design N
sk_logic.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:01:18 03/12/2008
// Design Name:
// Modul
mst_logic.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 15:27:54 01/04/2008
// Design Name:
// Modul
so_logic.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:06:44 01/05/2008
// Design Name:
// Modul
ctrl_logic.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:55:08 12/29/2007
// Design Name:
// Modul
gid_logic.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: sdmy
// Engineer: freedom
//
// Create Date: 14:56:53 12/29/2007
// Design Name
61_logic.vhd
library IEEE;
use IEEE.std_logic_1164.all;
package logic_pack is
function resolve(s : std_ulogic_vector) return std_ulogic;
SUBTYPE logic is resolve std_ulogic;
TYPE logic_vector IS ARRAY