mst_logic.v

链路铜梁调整机制的实现方案

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:27:54 01/04/2008 
// Design Name: 
// Module Name:    MST_logic 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module MST_logic(clk_125, resetn, en, ctrl_in, Mst_out);
    input clk_125;
    input resetn;
    input en;
    input [3:0] ctrl_in;
    output Mst_out;
    reg Mst_out;
	 
	 reg [3:0] state;
	 
	 parameter p_fixed=4'h0;
	 parameter p_add=4'h1;
	 parameter p_norm=4'h2;
	 parameter p_eos=4'h3;
	 parameter p_idle=4'h5;
	 parameter p_dnu=4'hf;
	 

always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)  state<=p_fixed;
    else    if(!en)    state<=state;
    else    
	      case(state)//parallel case
		   p_fixed:    begin
		                   if(ctrl_in==p_idle)    state<=p_idle;
								 else    state<=state;
						   end
		   p_add:      begin
		                   if(ctrl_in==p_fixed)    state<=p_fixed;
								 else    if(ctrl_in==p_eos)    state<=p_eos;
								 else    state<=state;
						   end
		   p_norm:     begin   
								     case(ctrl_in)//parallel case
									  p_fixed:   state<=p_fixed;
									  p_eos:     state<=p_eos;
									  p_idle:    state<=p_idle;    
									  p_dnu:     state<=p_dnu;
									  p_norm:    state<=state;									  
									  endcase
						   end
		   p_eos:      begin
								     case(ctrl_in)//parallel case
									  p_fixed:   state<=p_fixed;
									  p_norm:    state<=p_norm;
									  p_idle:    state<=p_idle;
									  p_dnu:     state<=p_dnu;
									  p_eos:     state<=state;
									  endcase
						   end	
		   p_idle:     begin
		                   if(ctrl_in==p_fixed)    state<=p_fixed;
								 else    if(ctrl_in==p_add)    state<=p_add;
								 else    state<=state;
						   end
		   p_dnu:      begin
								     case(ctrl_in)//parallel case
									  p_fixed:   state<=p_fixed;
									  p_norm:    state<=p_norm;
									  p_eos:     state<=p_eos;
									  p_dnu:     state<=p_dnu;
									  endcase
						   end	
         default:    state<=p_fixed;		
		  endcase
end

always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    Mst_out<=1;
	 else    if(!en)    Mst_out<=Mst_out;
	 else    
	     case(state)
		  p_fixed:   Mst_out<=1;
		  p_add:     Mst_out<=1;
		  p_norm:    Mst_out<=0;
		  p_eos:     Mst_out<=0;
		  p_idle:    Mst_out<=1;
		  p_dnu:     Mst_out<=1;
		  default:   Mst_out<=1;		  
		  endcase
end

endmodule