control_counter.v

来自「链路铜梁调整机制的实现方案」· Verilog 代码 · 共 78 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:01:54 12/26/2007 
// Design Name: 
// Module Name:    counter_16 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module control_counter(clk_125, resetn, en, count1, count2, c_out1, c_out2);
    input clk_125;
    input resetn;
    input en;
    output [3:0] count1;
	 output [7:0] count2;
	 output c_out1;
	 output c_out2;
	 
	 
	 reg [3:0] count1;
	 reg [7:0] count2;
	 reg c_out1;
	 reg c_out2;
	 
	 parameter p_mfi_1=4'hf;
	 parameter p_mfi_2=8'hff;
	 
always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)
	     begin
		      count1<=4'h0;
				count2<=8'h00;
				c_out1<=0;
				c_out2<=0;
		  end
    else    if(!en)
	     begin
		      count1<=4'h0;
				count2<=8'h00;
				c_out1<=0;
				c_out2<=0;
		  end
    else    if((count1==p_mfi_1)&&(count2==p_mfi_2))
	     begin
	         count1<=4'h0;
				count2<=8'h00;
				c_out2<=1;
				c_out1<=1;
        end
    else    if(count1==p_mfi_1)
	     begin
            count1<=4'h0;
				count2<=count2+1'b1; 
            c_out1<=1;
            c_out2<=0; 				
		  end
    else
	     begin
		      count1<=count1+1'b1;
				count2<=count2;
				c_out1<=0;
				c_out2<=0;
		  end
end
endmodule