gid_logic.v

链路铜梁调整机制的实现方案

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: sdmy
// Engineer: freedom
// 
// Create Date:    14:56:53 12/29/2007 
// Design Name: lcas
// Module Name:    gid_logic 
// Project Name: gif generator
// Target Devices: virtex2p
// Tool versions: ise 9.1i
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module gid_logic(clk_125, resetn, en, gid_out);
    input clk_125;
    input resetn;
    input en;
    output gid_out;
	 reg gid_out;
	 
	 reg reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7,reg8;
	 reg reg9,reg10,reg11,reg12,reg13,reg14;
	 
always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    gid_out<=0;
	 else    if(!en)    gid_out<=0;
	 else    gid_out<=reg0;
end

always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)
	     begin
		      reg0<=1;    reg1<=1;    reg2<=1;
				reg3<=1;    reg4<=1;    reg5<=1;
				reg6<=1;    reg7<=1;    reg8<=1;
				reg9<=1;    reg10<=1;   reg11<=1;
				reg12<=1;   reg13<=1;   reg14<=1;
		  end
    else    if(!en)
	     begin
		      reg0<=1;    reg1<=1;    reg2<=1;
				reg3<=1;    reg4<=1;    reg5<=1;
				reg6<=1;    reg7<=1;    reg8<=1;
				reg9<=1;    reg10<=1;   reg11<=1;
				reg12<=1;   reg13<=1;   reg14<=1;
		  end
    else    
	      begin
		      reg0<=reg1;    reg1<=reg2;    reg2<=reg3;
				reg3<=reg4;    reg4<=reg5;    reg5<=reg6;
				reg6<=reg7;    reg7<=reg8;    reg8<=reg9;
				reg9<=reg10;    reg10<=reg11;   reg11<=reg12;
				reg12<=reg13;   reg13<=reg14;   reg14<=reg0^reg13;
		  end
end
endmodule