frame_logic.v

链路铜梁调整机制的实现方案

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 	sdmy
// Engineer:   freedom
// 
// Create Date:    14:41:02 12/23/2007 
// Design Name:    lcas,
// Module Name:    out_logic 
// Project Name:   lcas
// Target Devices: virtex 2p
// Tool versions:  ise 9.1i
// Description:    the frequence is 8MHz,the period is 125us,the second MFI is 0 to 16
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module frame_logic(clk_125, resetn, en, mfi_1, mfi_2, sq, ctrl, gid, 
                   Mst_in_so, crc_8, RS_Ack_so, d_out);
    input clk_125;
    input resetn;
    input en;
    input [3:0] mfi_1;
    input [7:0] mfi_2;
    input [7:0] sq;
    input [3:0] ctrl;
    input gid;
	 input [7:0] Mst_in_so;//from this source to another sink 
	 input [7:0] crc_8;
	 input RS_Ack_so;//from this source to another sink 
    output [7:0] d_out;
	 reg [7:0]d_out;

	 
	 parameter p0=4'h0;
	 parameter p1=4'h1;
	 parameter p2=4'h2;
	 parameter p3=4'h3;
	 parameter p4=4'h4;
	 parameter p5=4'h5;
	 parameter p6=4'h6;
	 parameter p7=4'h7;
	 parameter p8=4'h8;
	 parameter p9=4'h9;
	 parameter p10=4'ha;
	 parameter p11=4'hb;
	 parameter p12=4'hc;
	 parameter p13=4'hd;
	 parameter p14=4'he;
	 parameter p15=4'hf;

	 
always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    d_out<=8'h00;
	 else if(!en)    d_out<=8'h00;
    else    case(mfi_1)//parallel case
	     p0:    d_out<={mfi_2[7:4],mfi_1};
        p1:    d_out<={mfi_2[3:0],mfi_1};
        p2:    d_out<={ctrl,mfi_1};	  
        p3:    d_out<={3'h0,gid,mfi_1};
        p4:    d_out<={4'h0,mfi_1};
        p5:    d_out<={4'h0,mfi_1};
	     p6:    d_out<={crc_8[7:4],mfi_1};
	     p7:    d_out<={crc_8[3:0],mfi_1};
	     p8:    d_out<={Mst_in_so[7:4],mfi_1};
	     p9:    d_out<={Mst_in_so[3:0],mfi_1};
	     p10:   d_out<={3'h0,RS_Ack_so,mfi_1};
	     p11:   d_out<={4'h0,mfi_1};		  
	     p12:   d_out<={4'h0,mfi_1};		  
	     p13:   d_out<={4'h0,mfi_1};		  
        p14:   d_out<={sq[7:4],mfi_1};
        p15:   d_out<={sq[3:0],mfi_1};
        default:   	d_out<=8'h00;
        endcase
end
endmodule