so_logic.v

链路铜梁调整机制的实现方案

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:06:44 01/05/2008 
// Design Name: 
// Module Name:    So_logic 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module So_logic(clk_125, resetn, enable, Lcas_m, Mst_in_sk, Mst_in_so, RS_Ack_sk, 
                RS_Ack_so, sq_number, Flag_vcg, flag_sq, M_status, M_add, M_rem, 
					 d_out, f_vcg, c_out2, RS_Ack_out);
    input clk_125;//system clock ,8000kHz
    input resetn;//system asynchronous reset,low level valible
    input enable;//enable signal
    input Lcas_m;//lcas or non-lcas mode,1:lcas;0:non-lcas
    input Mst_in_sk;//this signal is from this member sink for this member
	 input [7:0] Mst_in_so;////this signal is to another member source,for 8 member
    input RS_Ack_sk;//this signal is from this member sink
	 input RS_Ack_so;//this signal is to another member source
	 input [7:0] sq_number;//squence number
	 input Flag_vcg;//vcg adjusting flag
	 input flag_sq;//weather or not ,it has the maxium squence number
	 input M_status;//Member status ,using or not 
    input M_add;//add ,from manamgement
    input M_rem;//remove,from management
    output [7:0] d_out;//output the frame 
	 output f_vcg;//to vcg controllor
	 output c_out2;//
	 output RS_Ack_out;//to vcg controllor
 
	 
	 wire [3:0] MFI_1;
	 wire [7:0] MFI_2;
	 wire c_out1;
	 wire [3:0] ctrl;
	 wire gid;
	 wire [7:0] CRC_8;
	 
control_counter MFI_logic(.clk_125(clk_125),.resetn(resetn),.en(enable),
								  .count1(MFI_1),.count2(MFI_2),.c_out1(c_out1),
								  .c_out2(c_out2));
								  
ctrl_logic      CTRL_logic(.clk_125(clk_125),.resetn(resetn),.Lcas_m(Lcas_m),
                           .en(c_out1),.M_add(M_add),.M_rem(M_rem),
									.Flag_vcg(Flag_vcg),.Mst_in(Mst_in_sk),.M_status(M_status),
									.flag_sq(flag_sq),.ctrl_out(ctrl),.f_vcg(f_vcg));	
									
gid_logic       GID_logic(.clk_125(clk_125),.resetn(resetn),.en(c_out1),
                          .gid_out(gid));

crc_8_logic     CRC_logic(.clk_125(clk_125),.resetn(resetn),.en(enable),
                          .H4_msb(d_out[7:4]),.mfi_1(MFI_1),.crc_8_out(CRC_8));
								  
RS_Ack_So       RS_Ack_So(.clk_125(clk_125),.resetn(resetn),.en(c_out1),
                          .RS_Ack_sk(RS_Ack_sk),.present_ctrl(ctrl),.RS_Ack_out(RS_Ack_out));
								  
frame_logic     FRAME_logic(.clk_125(clk_125),.resetn(resetn),.en(enable),
                            .mfi_1(MFI_1),.mfi_2(MFI_2),.sq(sq_number),
									 .ctrl(ctrl),.gid(gid),.Mst_in_so(Mst_in_so),
									 .crc_8(CRC_8),.RS_Ack_so(RS_Ack_so),.d_out(d_out));
									 

endmodule