ctrl_logic.v

链路铜梁调整机制的实现方案

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:55:08 12/29/2007 
// Design Name: 
// Module Name:    ctrl_logic 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ctrl_logic(clk_125, resetn, en, Lcas_m, M_add, M_rem, 
                  Flag_vcg, Mst_in, M_status, flag_sq,
						ctrl_out, f_vcg);
    input clk_125;
    input resetn;
	 input Lcas_m;//lcas or no-lcas,0:no lcas;1:lcas
    input en;
    input M_add;//add from managment
    input M_rem;//remove from managment
    input Flag_vcg;//the flag of the whole vcg,wether or not in adjusting
    input Mst_in;//0:ok ;1:fail
	 input M_status;
	 input flag_sq;//the flag of maxium sq 
	 
    output [3:0] ctrl_out;//member status,to sink
	 output f_vcg;//this signal is the flag of vcg adjust,1:adjusting;0:not adjusting,it only present this member 
	 reg f_vcg;
	 reg [3:0] ctrl_out;
    
	 reg [3:0] state;
	 reg [1:0] l_state;
	 reg Flag_vc;
	 reg [2:0] counter_f;
	 
	 parameter p_remv=4'ha;
	 parameter p_fixed=4'h0;
	 parameter p_add=4'h1;
	 parameter p_norm=4'h2;
	 parameter p_eos=4'h3;
	 parameter p_idle=4'h5;
	 parameter p_dnu=4'hf;
	 
	 parameter p_keep=3'h4;




always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    state<=p_fixed;
	 else    if(!en)    state<=state;
	 else
	     case(state)//parallel case
		  p_fixed:    begin
		                  if(Lcas_m)    state<=p_idle;
								else    state<=state;
						  end
		  p_add:      begin
		                  if(!Lcas_m)    state<=p_fixed;
								else    if(Flag_vcg&&Flag_vc&&M_status)
                            begin
                                if(M_rem)    state<=p_remv;
										  else    if(!Mst_in)    state<=p_norm;
										  else    state<=state;
									 end
								else    state<=state;
						  end
		  p_norm:     begin
		                  if(!Lcas_m)    state<=p_fixed;
								else    if(!Flag_vc&&M_status)
								    begin
									     if((!Flag_vcg)&&M_rem)    state<=p_remv;
										  else    if(Mst_in)    state<=p_dnu;
										  else    state<=state;
									 end
								else    state<=state;
						  end
		  p_idle:     begin
								if(!Lcas_m)    state<=p_fixed;
								else    if((!Flag_vcg)&&(!Flag_vc)&&M_add&&!M_status)    state<=p_add;
								else    state<=state;
						  end
		  p_remv:     begin
		                  if(!Lcas_m)    state<=p_fixed;
								else    if(Flag_vcg&&Flag_vc&&Mst_in&&M_status)    state<=p_idle;
								else    state<=state;
						  end
		  p_dnu:      begin
		                  if(!Lcas_m)    state<=p_fixed;
								else    if((!Flag_vcg)&&(!Flag_vc)&&M_status)
								    begin
									     if(M_rem)    state<=p_remv;
										  else    if(!Mst_in)    state<=p_norm;
										  else    state<=state;
									 end
								else    state<=state;
						  end
		  default:    state<=p_fixed;					  
		  endcase
end

always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    l_state<=p_fixed;
	 else    if(en)    l_state<=state;
	 else    l_state<=l_state;
end


always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    ctrl_out<=p_fixed;
	 else    if(!en)    ctrl_out<=ctrl_out;
	 else
	     case(state)//parallel case
		  p_fixed:    ctrl_out<=p_fixed;
		  p_add:      ctrl_out<=p_add;
		  p_norm:     begin
		                 if(flag_sq)    ctrl_out<=p_eos;
							  else    ctrl_out<=p_norm;
						  end
		  p_idle:     ctrl_out<=p_idle;
		  p_remv:     ctrl_out<=p_idle;
		  p_dnu:      ctrl_out<=p_dnu;
		  default:    ctrl_out<=p_fixed;
		  endcase
end

always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    
	     begin
		      Flag_vc<=0;
				f_vcg<=0;
		  end
	 else    if(!Lcas_m)
        begin
    		  Flag_vc<=0;
			  f_vcg<=0;
		  end
	 else    if(!en)
        begin
    		  Flag_vc<=Flag_vc;
			  f_vcg<=f_vcg;
		  end
    else    
	     case(state)
		  p_add:    begin
		                Flag_vc<=1;
							 f_vcg<=1;
						end
		  p_norm:   begin
							 if(counter_f==p_keep)
							     begin
								      Flag_vc<=0;
							         f_vcg<=0;
								  end
							 else
							     begin
								      Flag_vc<=1;
										f_vcg<=1;
								  end
						end
		  p_idle:   begin
							 if(counter_f==p_keep)
							     begin
								      Flag_vc<=0;
							         f_vcg<=0;
								  end
							 else
							     begin
								      Flag_vc<=1;
										f_vcg<=1;
								  end
						end		  
		  p_remv:   begin
		                Flag_vc<=1;
							 f_vcg<=1;
					   end
		  p_dnu:    begin
		                f_vcg<=0;
                      if(counter_f==p_keep)    Flag_vc<=0;
							 else    Flag_vc<=1;
						end
		  default:  begin
		                Flag_vc<=0;
							 f_vcg<=0;
					   end
		  endcase
end


always @(posedge clk_125 or negedge resetn)
begin
    if(!resetn)    counter_f<=0;
	 else    if(!en)   counter_f<=counter_f;
    else    if((state==p_idle)&&((l_state==p_remv)||(l_state==p_fixed))||((l_state==p_dnu)&&(state==p_norm))||((l_state==p_add)&&(state==p_norm)))    counter_f<=1;
	 else    if(counter_f==p_keep)    counter_f<=counter_f;
    else    if(counter_f!=3'h0)    counter_f<=counter_f+1'b1;
	 else    counter_f<=0;
end
endmodule