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untitled.cdf
JedecChain;
FileRevision(JESDxxA);
/* NoviceMode */
/* Active Mode BS */
/* Mode BS */
/* Cable ParallelIII lpt1 200000 */
P ActionCode(Cfg)
Device
PartName(xc9572)
File("D:\FPGA\xc_
cpu_3rd_package.txt
-- Third Party Package containing functions for Bit_Vector operations
-- download from: www.fpga.com.cn & www.pld.com.cn
-- Cypress Semiconductor WARP 2.0
--
-- Copyright Cypress Semicondu
chess_clock.txt
-- Chess Clock
-- some expressions can not be synthetized,only for Simulation. (such as "AFTER 500 ms")
-- download from: www.fpga.com.cn & www.pld.com.cn
PACKAGE chesspack IS
SUBTYPE hour
readme.txt
README file: XAPP204 VHDL Reference Design
==========================================
Date: Wed. September 28, 1999
Updates: 12/10/99 - JLB - Compilation with FPGA Express 3.3 and Alliance 2.1i S
decode_2.v
//
// Module: DECODE_2
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
decode_3.v
//
// Module: DECODE_3
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
decode_4.v
//
// Module: DECODE_4
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
decode_1.v
//
// Module: DECODE_1
// Design: CAM_Top
// Verilog code: RTL / Combinatorial
//
// Synthesis_tool Synopsys FPGA Express ver. 3.2
// Enable Synthesis Option: Verilog Pre-procesor
棋类比赛计时时钟.txt
-- Chess Clock
-- some expressions can not be synthetized,only for Simulation. (such as "AFTER 500 ms")
-- download from: www.fpga.com.cn & www.pld.com.cn
PACKAGE chesspack IS
SUBTYPE hour
ram.xco
# BEGIN Project Options
SET flowvendor = Other
SET vhdlsim = True
SET verilogsim = False
SET workingdirectory = D:\Develop\PQS\FPGA\fft_test
SET speedgrade = -4
SET simulationfiles = Behavioral
SET as