decode_1.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	DECODE_1
// Design: 	CAM_Top
// Verilog code:	 RTL / Combinatorial
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.2 
//		        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: Decode 1 bit address into 2 binary bits
//		Generate an ENABLE bus
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Transalted to Verilog by: Brian Philofsky / Xilinx Design Center
// Date: July 23, 1999
// Version: 1.0
//
// History: 
// 	1. 09/08/99 BP - Translated to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-

module DECODE_1 (ADDR,
		 ENABLE,
		 BINARY_ADDR);
   
   input        ADDR;
   input        ENABLE;

   output [1:0] BINARY_ADDR;

   reg [1:0] 	BINARY_ADDR;
   
   // wire VCC : std_logic;
   // wire GND : std_logic;


   // assign VCC <= ENABLE;
   // assign GND <= 1'b0;

   // Create the write enable signal for each CAM_RAMB4

   always @(ADDR or ENABLE)
      case (ADDR)
         1'b0: BINARY_ADDR = {1'b0, ENABLE};
	 1'b1: BINARY_ADDR = {ENABLE, 1'b0};
      endcase // case(ADDR[0])
   
endmodule