decode_4.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	DECODE_4
// Design: 	CAM_Top
// Verilog code:	 RTL / Combinatorial
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.2 
//		        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: 	Decode 4 bits address into 16 binary bits
//		Generate an ENABLE bus
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Translated to Verilog by: Brian Philofsky / Xilinx Design Center
// Date: July 23, 1999
// Version: 1.0
//
// History: 
// 	1. 09/08/99 BP - Translated to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-

module DECODE_4 (ADDR,
		 ENABLE,
		 BINARY_ADDR);

   input [3:0] ADDR;
   input       ENABLE;

   output [15:0] BINARY_ADDR;

   reg [15:0] 	 BINARY_ADDR;
   
   
   // wire VCC;
   // wire GND;


   // assign VCC = ENABLE;
   // assign GND = 1'b0;

   // Create the write enable signal for each CAM_RAMB4

   always @(ADDR or ENABLE)
     case (ADDR)
       4'b0000: BINARY_ADDR <= {15'h0000, ENABLE};
       4'b0001: BINARY_ADDR <= {14'h0000, ENABLE, 1'h0};
       4'b0010: BINARY_ADDR <= {13'h0000, ENABLE, 2'h0};
       4'b0011: BINARY_ADDR <= {12'h000, ENABLE, 3'h0};
       4'b0100: BINARY_ADDR <= {11'h000, ENABLE, 4'h0};
       4'b0101: BINARY_ADDR <= {10'h000, ENABLE, 5'h00};
       4'b0110: BINARY_ADDR <= {9'h000, ENABLE, 6'h00};
       4'b0111: BINARY_ADDR <= {8'h00, ENABLE, 7'h00};
       4'b1000: BINARY_ADDR <= {7'h00, ENABLE, 8'h00};
       4'b1001: BINARY_ADDR <= {6'h00, ENABLE, 9'h000};
       4'b1010: BINARY_ADDR <= {5'h00, ENABLE, 10'h000};
       4'b1011: BINARY_ADDR <= {4'h0, ENABLE, 11'h000};
       4'b1100: BINARY_ADDR <= {3'h0, ENABLE, 12'h000};
       4'b1101: BINARY_ADDR <= {2'h0, ENABLE, 13'h0000};
       4'b1110: BINARY_ADDR <= {1'h0, ENABLE, 14'h0000};
       4'b1111: BINARY_ADDR <= {ENABLE, 15'h0000};
     endcase // case(ADDR)
   
									
endmodule