readme.txt

Using Block RAM for High-Performance Read.Write Cams

README file: XAPP204 VHDL Reference Design
==========================================

Date: Wed. September 28, 1999
Updates: 12/10/99 - JLB - Compilation with FPGA Express 3.3 and Alliance 2.1i SP3

Author: Jean-Louis Brelet / Xilinx

File Name:
----------
  xapp204_vhdl.zip, xapp204_vhdl.tar.Z

Description:
------------
  Contains the following files
	readme.txt	: This file

	CAM_Top.ucf	: Alliance Timing Constraints example for a CAM 32 words x 8 bits at 66 MHz 
	
	CAM_top.vhd : Top VHDL wrapper file for testing CAM_generic_8s.vhd (Default CAM 32x8)
	CAM_generic_8s.vhd : Top level of the reference design (Parametrizable word width and depth)
	CAM_RAMB4.vhd : CAM module 16 x 8-bit
	Init_8_RAM16Xx1s.vhd : Basic Building block instantiating 8 RAM16x1s
	Init_RAMB4_S1_S16.vhd : Basic Building Block instantiating RAMB4
	Encode_4_LSB.vhd : Encode a 16-bit binary address into 4 bits
	Encode_X_MSB.vhd : (available for 4, 3, 2 and 1 bit) 
			Encode binary address into a X bits bus and add the LSB address
	Decode_X.vhd : (available for 4, 3, 2 and 1 bit) Decode X bits into a binary address

	TB_CAM_RAMB4.vhd : Test Bench for the module CAM_RAMB4.vhd

Platform:
---------
  All

Installation/Use:
-----------------
  Use 'unzip' on the .zip file and 'uncompress' followed by 'tar -xvf' on the .tar.Z file.

Parametrizable VHDL code:
-------------------------
  Edit "CAM_top.vhd" 
	Modify the "addr_width" to the required number of address lines (default = 5 address lines)
	Modify the "nb_cam_16words" to the equivalent number of CAM 16 words blocks (default = 2 blocks)

  Edit "CAM_generic_word.vhd"
	Remove the comments of the corresponding "Encode_X_MSB" and "Decode_X" instantiation
	By default the CAM 32 x 8 uses the Encode_1_MSB and Decode_1 instances.
(Do NOT change or comment the Encode_4_LSB module, which is required by each basic CAM 16 word module)

Functionnal Simulation:
-----------------------
   The design has been tested using Model Technology ModelSim EE 5.3a
	A testbench for the basic CAM_RAMB4.vhd is provided as example.

	Create a link to the UNISIM vhdl models library. 
	(Please see documentation about functionnal simulation)
	Compile all the vhdl files included TB_CAM_RAMB4 (Test Bench)
	Load TB_CAM_RAMB4 and run the simulation. (Basic Write and Read operations)

  
Synthesis:
----------
  The design has been tested using Synopsys FPGA Express ver. 3.3
	In the "Create Implementation" Template: 
		Device = XCV100EPQ240
		Speed grade = -6
		Preserve Hierarchy = On
		Clock frequency = 66 MHz

	Export Netlist WITHOUT timing 

Implementation:
---------------
   The design has been tested using Xilinx Alliance ver. 2.1i SP3 targetting XCV100 or XCV100E
	(Please see the Alliance 2.1i documentation about how to use the tools)

	Use the "CAM_Top.ucf" file as timing constraints file 
	
	Option: Constraint files with placement are available as example
	(Modify Init_8_RAM16x1s.vhd module to use RLOC)

	In the "Implementation / Optimize and Map" template:
		Select the Map option = Pack I/O registers into IOB for Inputs & Outputs
	Suggested High Place and Route effort

	MAP shows the following warning in the "map.mrp" report file:
	WARNING: Blockcheck: "Dangling BLKRAM output. Pin DOA0 of comp .../RAMB4 is nor connected"
	This warning can be ignored because the Block SelectRAM memories have no connection on 
	the port A output. (Use as Write port only)


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