decode_2.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	DECODE_2
// Design: 	CAM_Top
// Verilog code:	 RTL / Combinatorial
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.2 
//		        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: Decode 2 bits address into 4 binary bits
//		Generate an ENABLE bus
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Converted to Verilog by: Brian Philofsky / Xilinx Design Center
// Date: July 23, 1999
// Version: 1.0
//
// History: 
// 	1. 09/09/99 BP - Converted to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-


module DECODE_2 (ADDR, ENABLE, BINARY_ADDR);

   input [1:0] ADDR;
   input       ENABLE;

   output [3:0] BINARY_ADDR;

   reg [3:0] 	BINARY_ADDR;
   

   // wire VCC;
   // wire GND;

   // assign VCC = ENABLE;
   // assign GND = 1'b0;

   // Create the write enable signal for each CAM_RAMB4

   always @(ADDR or ENABLE)
     case (ADDR[1:0])
       2'b00: BINARY_ADDR = {3'b000, ENABLE};
       2'b01: BINARY_ADDR = {2'b00, ENABLE, 1'b0};
       2'b10: BINARY_ADDR = {1'b0, ENABLE, 2'b00};
       2'b11: BINARY_ADDR = {ENABLE, 3'b000};
     endcase // case(ADDR[1:0])

endmodule // DECODE_2