decode_3.v

Using Block RAM for High-Performance Read.Write Cams

//
// Module: 	DECODE_3
// Design: 	CAM_Top
// Verilog code:	 RTL / Combinatorial
//
// Synthesis_tool	Synopsys FPGA Express ver. 3.2 
//		        Enable Synthesis Option: Verilog Pre-procesor
//
// Description: Decode 3 bits address into 8 binary bits
//		Generate an ENABLE bus
//
// Device: 	VIRTEX Families
//
// Created by: Jean-Louis BRELET / XILINX - VIRTEX Applications
// Translated to Verilog by: Brian Philofsky / Xilinx Design Center
// Date: July 23, 1999
// Version: 1.0
//
// History: 
// 	1. 09/09/99 BP - Translated to Verilog
//
//   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
//                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
//                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
//                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
//
//  Copyright (c) 1999 Xilinx, Inc.  All rights reserved.
//////////////////////////////////////////////////////////////////////////////////////////////////////-


module DECODE_3 (ADDR, ENABLE, BINARY_ADDR);

   input [2:0] ADDR;
   input       ENABLE;

   output [7:0] BINARY_ADDR;

   reg [7:0] 	BINARY_ADDR;

   // wire VCC;
   // wire GND;

   // assign VCC = ENABLE;
   // assign GND = 1'b0;

   // Create the write enable signal for each CAM_RAMB4

   always @(ADDR or ENABLE)
     case (ADDR[2:0])
       3'b000: BINARY_ADDR = {7'h00, ENABLE};
       3'b001: BINARY_ADDR = {6'h00, ENABLE, 1'h0};
       3'b010: BINARY_ADDR = {5'h00, ENABLE, 2'h0};
       3'b011: BINARY_ADDR = {4'h0, ENABLE, 3'h0};
       3'b100: BINARY_ADDR = {3'h0, ENABLE, 4'h0};
       3'b101: BINARY_ADDR = {2'h0, ENABLE, 5'h00};
       3'b110: BINARY_ADDR = {1'h0, ENABLE, 6'h00};
       3'b111: BINARY_ADDR = {ENABLE, 7'h00};
     endcase // case(ADDR[2:0])
   
endmodule // DECODE_3