代码搜索:FPGA
找到约 10,000 项符合「FPGA」的源代码
代码结果 10,000
www.eeworm.com/read/418434/10945875
qmsg prev_cmp_flow_led.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0
www.eeworm.com/read/418434/10945892
qmsg flow_led.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0
www.eeworm.com/read/464438/7158443
ref hdllib.ref
EN digital_clk NULL E:/DEMO_FPGA/digital_clk_timesim.vhd sub00/vhpl00 1111691296
AR dfgf testbench_arch E:/DEMO_FPGA/dfgf.timesim_vhw sub00/vhpl03 1111691299
EN dfgf NULL E:/DEMO_FPGA/dfgf.timesim_v
www.eeworm.com/read/457944/7315158
rpt sub_tdm.tan.rpt
Timing Analyzer report for sub_tdm
Mon Oct 30 12:04:26 2006
Version 5.0 Build 168 06/22/2005 Service Pack 1.04 SJ Full Version
---------------------
; Table of Contents ;
--------------------
www.eeworm.com/read/447996/7542366
ref hdpdeps.ref
V1 32
FL G:/vijay_FPGA_LAB/alu_2bit/buff.vhd 2006/02/14.13:58:34
EN work/BUFF FL G:/vijay_FPGA_LAB/alu_2bit/buff.vhd \
PB ieee/STD_LOGIC_1164 PB ieee/STD_LOGIC_ARITH PB ieee/STD_LO
www.eeworm.com/read/447993/7542516
sig 11bit_add.sig
// PROMGEN: Xilinx Prom Generator G.35
// Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved.
DATE 01/21/06-12:31
SOURCE g:\vijay_fpga_lab\1bit_add//11bit_add.mcs
DEVICE XCF01S
www.eeworm.com/read/328536/13021508
v test_cpe_top.v
module test_cpe_top();
module cpe_top (
// DSP EMIF port
.DSP_AAWE_N,
.DSP_A0E_N,
.DSP_ACE3_N,
.DSP_AED, // DSP data bus, 16bit
.DSP_AE
www.eeworm.com/read/315669/13538550
prj cmos_fifo_usb_syn.prj
#add_file options
add_file -verilog "H:/fpga_test/cmos_fifo_usb/smartgen/two_port1280x8/two_port1280x8.v"
add_file -verilog "H:/fpga_test/cmos_fifo_usb/smartgen/usb_fifo32x16/usb_fifo32x16.v"
add_f
www.eeworm.com/read/315669/13538553
txt run_options.txt
#-- Synplicity, Inc.
#-- Version Synplify 8.8A1
#-- Project file H:\fpga_test\cmos_fifo_usb\synthesis\run_options.txt
#-- Written on Wed May 21 14:37:58 2008
#add_file options
add_file -veril
www.eeworm.com/read/315669/13538556
srr cmos_fifo_usb.srr
#Build: Synplify 8.8A1, Build 015R, Apr 16 2007
#install: C:\Libero\Synplify\Synplify_88A1
#OS: Windows XP 5.1
#Hostname: ZHOUHUAGOU
#Implementation: synthesis
#Wed May 21 14:37:58 2008
$