cmos_fifo_usb_syn.prj

cmos数据到fifo再到usb的fifo部分程序(68013a)

#add_file options
add_file -verilog "H:/fpga_test/cmos_fifo_usb/smartgen/two_port1280x8/two_port1280x8.v"
add_file -verilog "H:/fpga_test/cmos_fifo_usb/smartgen/usb_fifo32x16/usb_fifo32x16.v"
add_file -verilog "H:/fpga_test/cmos_fifo_usb/hdl/cmos_fifo.v"

#device options
set_option -technology ProASIC3
set_option -part A3P060
set_option -vlog_std v2001

#compilation/mapping options
set_option -symbolic_fsm_compiler true

#compilation/mapping options
set_option -frequency 100.000

#simulation options
impl -active "synthesis"
project -result_file "H:/fpga_test/cmos_fifo_usb/synthesis/cmos_fifo_usb.edn"