代码搜索：FPGA
找到约 10,000 项符合「FPGA」的源代码
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txt taxi.txt
多功能计程车计价器的设计
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qmsg fpga_dsp_portlink.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/167918/9947582
vhd dsp1_ram_module.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
entity dsp_ram_module is
port(
-------------------------------------Pins between dsp and
www.eeworm.com/read/424812/10410696
tcl uart_version2.tcl
########## Tcl recorder starts at 03/06/09 23:46:51 ##########
set version "7.0"
set proj_dir "F:/NEW_UART/UART0_2"
cd $proj_dir
# Get directory paths
set pver $version
regsub -all {\.} $p
www.eeworm.com/read/260117/11746484
tcl uart_v.tcl
########## Tcl recorder starts at 07/17/07 10:46:38 ##########
set version "6.1"
set proj_dir "F:/custmor training/Code test/2/1"
cd $proj_dir
# Get directory paths
set pver $version
regsu
www.eeworm.com/read/345513/11810535
work__info
m255
13
cModel Technology
dE:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec
T_opt
V1?n;Q1Qb?XT9gl2iECM]G0
04 14 4 work test_match_rec
www.eeworm.com/read/345513/11810575
_info
m255
13
cModel Technology
dE:\wangqiuju\study\researchproject\FPGA\book_onFPGA\wireless-FPGA-design-code\Verilog-code\c12_0\12-2_0\match_rec
T_opt
V1?n;Q1Qb?XT9gl2iECM]G0
04 14 4 work test_match_rec
www.eeworm.com/read/345513/11810611
log sap.log
Synplicity Xilinx Technology Mapper, Version 8.8.0p, Build 069R, Built Apr 17 2007 19:41:05
Copyright (C) 1994-2007, Synplicity Inc. All Rights Reserved
Product Version Version 8.8.0.4
Reading con
www.eeworm.com/read/18582/794824