dsp1_ram_module.vhd

FPGA与DSP的EMIFA口接口程序.在FPGA内分配了两块双BUFFER与DSP进行通信.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

entity dsp_ram_module is
port(
-------------------------------------Pins between dsp and FGPA-----------------------------------
		dsp_fpga_data	:	inout	std_logic_vector(31 downto 0);
		dsp_fpga_addr	:	in		std_logic_vector(20 downto 3);
		dsp_fpga_clk	:	in		std_logic;	
		dsp_fpga_we	:	in	std_logic;
		dsp_fpga_oe	:	in	std_logic;
		dsp_fpga_ce1	:	in	std_logic;		
		dsp_fpga_ext_int4	:	out std_logic;
		dsp_fpga_ext_int5	:	out std_logic;		
		dsp_fpga_ext_int6	:	out std_logic;
		dsp_fpga_ext_int7	:	out std_logic;
-------------------------------Pins between RAM and FGPA internal logic----------------------------
		gclk_o		:	in	std_logic;
		clk_rx		:	in	std_logic;
		addr_tx		:	in	std_logic_vector(12 downto 0);	
		addr_rx		:	in	std_logic_vector(12 downto 0);
		rx_offset_out			:	out	std_logic_vector(12 downto 0);
		dsp_ram_rx_dina		:	in	std_logic_vector(31 downto 0);	 	--ram_rx A port input data bus					
		dsp_ram_tx_douta	: out	std_logic_vector(31 downto 0));		--ram_tx A port output data bus	

end dsp_ram_module;

architecture Behavioral of dsp_ram_module is
---------------------------------------------------------------------------------------------------
component data_ram
    port (
    addra: IN std_logic_VECTOR(12 downto 0);
    addrb: IN std_logic_VECTOR(12 downto 0);
    clka: IN std_logic;
    clkb: IN std_logic;
    dina: IN std_logic_VECTOR(31 downto 0);
    doutb: OUT std_logic_VECTOR(31 downto 0);
    wea: IN std_logic);
end component;
---------------------------------------------------------------------------------------------------
component data_ram_tx
    port (
    addra: IN std_logic_VECTOR(12 downto 0);
    addrb: IN std_logic_VECTOR(12 downto 0);
    clka: IN std_logic;
    clkb: IN std_logic;
    dinb: IN std_logic_VECTOR(31 downto 0);
    douta: OUT std_logic_VECTOR(31 downto 0);
    doutb: OUT std_logic_VECTOR(31 downto 0);
    web: IN std_logic);
end component;
--------------------------------------------------------------------------------------------------- 
------------------------------ram_rx with dsp data & address signal-------------------------------
signal	dsp_to_fpga_data		:	std_logic_vector(31 downto 0);
signal	fpga_to_dsp_data		:	std_logic_vector(31 downto 0);
signal  	dsp_fpga_addr_reg   : std_logic_vector(20 downto 3);

signal 	dsp_ram_rx_addrb   	: std_logic_vector(12 downto 0); 	
signal	dsp_ram_rx_doutb	  	: std_logic_vector(31 downto 0);
----------------------------------ram_rx with dsp control signal----------------------------------
signal  	dsp_we_reg 			: std_logic;		 					--dsp write enable reg

signal  	dsp_ce1_reg1  		: std_logic;		 					--dsp read enable reg
signal  	dsp_ce1_reg2  		: std_logic;

signal  	dsp_ram_rx_web  	 	: 	std_logic;								--ram_rx write bport enable
signal	dsp_ram_rx_reg    	: 	std_logic_vector(1 downto 0);		--ram_rx interrupt register
signal	dsp_ram_rx_int    	: 	std_logic;					      	--ram_rx ex_interrupt signal
signal	dsp_ram_rx_int_en		:	std_logic;								--ram_rx int enable
------------------------------ram_tx with dsp data & address signal-------------------------------
signal 	dsp_ram_tx_addrb   	: 	std_logic_vector(12 downto 0);
signal 	dsp_ram_tx_doutb   	: 	std_logic_vector(31 downto 0);   
----------------------------------ram_tx with dsp control signal----------------------------------
signal  	dsp_ram_tx_web  	 	: 	std_logic;								--ram_tx_I write bport enable
signal	dsp_ram_tx_reg    	: 	std_logic_vector(1 downto 0);		--ram_tx_I interrupt register
signal	dsp_ram_tx_int    	: 	std_logic;					      	--ram_tx_I ex_interrupt signal
signal	dsp_ram_tx_int_en		:	std_logic:='0';						--ram_tx_I int enable

signal	rx_offset				:	std_logic_vector(12 downto 0);

																	  
begin

rx_offset_out(12 downto 0)	<=	rx_offset(12 downto 0);
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
U_RX_to_dsp : data_ram
        port map (
            addra => addr_rx(12 downto 0),
            addrb => dsp_ram_rx_addrb(12 downto 0),
            clka => clk_rx,
            clkb => dsp_fpga_clk,
            dina => dsp_ram_rx_dina(31 downto 0),	             
            doutb => dsp_ram_rx_doutb(31 downto 0),
            wea => '1'			--continuous write
            );
---------------------------------------------------------------------------------------------------
dsp_fpga_data(31 downto 0) <= fpga_to_dsp_data(31 downto 0) when (dsp_fpga_oe = '0' and dsp_ce1_reg2 = '0') else (others => 'Z');
---------------------------------------------------------------------------------------------------
P_latency_4:process(dsp_fpga_clk)
begin
if rising_edge(dsp_fpga_clk)	then
	dsp_fpga_addr_reg(20 downto 3)  	<= dsp_fpga_addr(20 downto 3);
	dsp_to_fpga_data(31 downto 0)  	<= dsp_fpga_data(31 downto 0);

	dsp_we_reg 	<= dsp_fpga_we or dsp_fpga_ce1; 	--DSP write enable
	dsp_ce1_reg1 	<= dsp_fpga_ce1;	--DSP output enable
	dsp_ce1_reg2 	<= dsp_ce1_reg1;
end if;
end process;	
---------------------------------------------------------------------------------------------------
dsp_ram_rx_addrb <= dsp_fpga_addr(15 downto 3);									  	    		  	 
---------------------------------------------------------------------------------------------------
---------------------------------------Write dsp register-----------------------------------------
P_write_dsp_reg:process(dsp_fpga_clk)
begin
if rising_edge(dsp_fpga_clk) then
   if dsp_fpga_ce1 = '0' and dsp_fpga_we = '0' then
		 if  dsp_fpga_addr(20 downto 14)="0000100" then			 
			 --DSP addr: 0x80008004	:	dsp_ram_tx_int_en
			 if dsp_fpga_addr(6 downto 3) = "0001" then		 
			     dsp_ram_tx_int_en <= dsp_fpga_data(0);
			 end if;

			 --DSP addr: 0x80008008	:	dsp_ram_rx_int_en
			 if dsp_fpga_addr(6 downto 3) = "0010" then		 
			     dsp_ram_rx_int_en <= dsp_fpga_data(0);
			 end if;
			 
			 --DSP addr: 0x80008020	:	rx_offset
			 if dsp_fpga_addr(6 downto 3) = "1000" then		 
			     rx_offset(12 downto 0) <= dsp_fpga_data(12 downto 0);
			 end if;				 
			 			 			 			 	 		
		 end if;
   end if;
end if;
end process;
--------------------------------------Read dsp register&ram--------------------------------------
P_dsp_read_ram:process(dsp_fpga_clk)
begin
if rising_edge(dsp_fpga_clk)	then
	if dsp_fpga_addr_reg(20 downto 16) =	"00000"	then
		fpga_to_dsp_data(31 downto 0) <= dsp_ram_rx_doutb(31 downto 0);
	elsif	dsp_fpga_addr_reg(20 downto 16) =	"00010"	then	
		fpga_to_dsp_data(31 downto 0) <= dsp_ram_tx_doutb(31 downto 0);
	elsif	dsp_fpga_addr_reg(20 downto 14) =	"0000100"	then	
			 
			 --DSP addr: 0x80008004	:	dsp_ram_tx_int_en
			 if dsp_fpga_addr_reg(6 downto 3) = "0001" then		 
			     fpga_to_dsp_data(31 downto 0) <=	x"0000000" & "000" & dsp_ram_tx_int_en;
			 
			 --DSP addr: 0x80008008	:	dsp_ram_rx_int_en
			 elsif dsp_fpga_addr_reg(6 downto 3) = "0010" then		
			     fpga_to_dsp_data(31 downto 0) <=	x"0000000" & "000" & dsp_ram_rx_int_en;

			 --DSP addr: 0x8000800C	:	dsp_ram_rx_reg
			 elsif dsp_fpga_addr_reg(6 downto 3) = "0011" then		 
			     fpga_to_dsp_data(31 downto 0) <=	x"0000000" & "00" & dsp_ram_rx_reg(1 downto 0);	
			
			 --DSP addr: 0x80008010:	dsp_ram_tx_reg 
			 elsif dsp_fpga_addr_reg(6 downto 3) = "0100" then		
			     fpga_to_dsp_data(31 downto 0) <=	x"0000000" & "00" & dsp_ram_tx_reg(1 downto 0);				 

			 --DSP addr: 0x80008020:	rx_offset 
			 elsif dsp_fpga_addr_reg(6 downto 3) = "1000" then		
			     fpga_to_dsp_data(31 downto 0) <=	x"0000" & "000" & rx_offset(12 downto 0);			 
			 
			 else
			 		 fpga_to_dsp_data(31 downto 0) <= x"12345678";
			 end if;
			 	
	else
		fpga_to_dsp_data(31 downto 0) <= x"12345678";
	end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
P_gen_dsp_ext_int4:process(clk_rx)		--PHY interrupt
begin
if rising_edge(clk_rx) then
	 if addr_rx(11 downto 0) = "111111111111" then   
	 		dsp_ram_rx_int <= '0';
	 else
	 		dsp_ram_rx_int <= '1';
  end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
P_dsp_ram_part_sel:process(clk_rx)
begin
if rising_edge(clk_rx) then
	if addr_rx(12) = '0' then
		dsp_ram_rx_reg(1 downto 0) <= "10";		
	elsif	addr_rx(12) = '1' then
	 	dsp_ram_rx_reg(1 downto 0) <= "01";
	else
		null;
	end if;	  
end if;
end process;
---------------------------------------------------------------------------------------------------
dsp_fpga_ext_int4 <=	dsp_ram_rx_int and dsp_ram_rx_int_en;
-----------------------------Logic between FPGA and dsp RX end------------------------------------
---------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------
--------------------------------Logic between FPGA and dsp TX-------------------------------------	
---------------------------------------------------------------------------------------------------
U_TX_ram : data_ram_tx
        port map (
            addra => addr_tx(12 downto 0),
            addrb => dsp_ram_tx_addrb(12 downto 0),
            clka => gclk_o,
            clkb => dsp_fpga_clk,
            dinb => dsp_to_fpga_data(31 downto 0),
            douta => dsp_ram_tx_douta(31 downto 0),
            doutb => dsp_ram_tx_doutb(31 downto 0),
            web => dsp_ram_tx_web);
---------------------------------------------------------------------------------------------------
dsp_ram_tx_addrb <= dsp_fpga_addr_reg(15 downto 3) when dsp_we_reg = '0' else
		   	    		  	 dsp_fpga_addr(15 downto 3);
---------------------------------------------------------------------------------------------------
P_dsp_ram_tx_web:process(dsp_fpga_clk)																	
begin
if rising_edge(dsp_fpga_clk) then
	if dsp_fpga_addr(20 downto 16) ="00010" and dsp_fpga_we = '0' and dsp_fpga_ce1='0' then
		dsp_ram_tx_web <= '1';					--ram_tx write enable (active high)
	else
		dsp_ram_tx_web <= '0';
	end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
P_gen_dsp_ext_int6:process(gclk_o)
begin
if rising_edge(gclk_o) then
	 if addr_tx(11 downto 0) = "111111111111"	then   
	 	dsp_ram_tx_int <= '0';	
	 else
	 	dsp_ram_tx_int <= '1';
   end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
P_dsp_ram_tx_part_sel:process(gclk_o)						 
begin
if rising_edge(gclk_o) then
	if addr_tx(12) = '0' then			
		dsp_ram_tx_reg(1 downto 0) <= "10";		
	elsif	addr_tx(12) = '1'	then	
	 	dsp_ram_tx_reg(1 downto 0) <= "01";			 
	else
		null;
	end if;	  
end if;						
end process;
---------------------------------------------------------------------------------------------------
dsp_fpga_ext_int6 <= dsp_ram_tx_int and dsp_ram_tx_int_en;																			 
---------------------------------------------------------------------------------------------------
end Behavioral;