fpga_dsp_portlink.map.qmsg

implemention of FPGA and DSP linking port, using Asynchronous mode

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 03 11:09:16 2008 " "Info: Processing started: Thu Jan 03 11:09:16 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FPGA_DSP_PortLink -c FPGA_DSP_PortLink " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FPGA_DSP_PortLink -c FPGA_DSP_PortLink" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_bustri1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lpm_bustri1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_bustri1-SYN " "Info: Found design unit 1: lpm_bustri1-SYN" {  } { { "lpm_bustri1.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/lpm_bustri1.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_bustri1 " "Info: Found entity 1: lpm_bustri1" {  } { { "lpm_bustri1.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/lpm_bustri1.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FPGA_DSP_PortLink_BiBus.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file FPGA_DSP_PortLink_BiBus.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FPGA_DSP_PortLink_BiBus " "Info: Found entity 1: FPGA_DSP_PortLink_BiBus" {  } { { "FPGA_DSP_PortLink_BiBus.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "COUT.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file COUT.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cout-SYN " "Info: Found design unit 1: cout-SYN" {  } { { "COUT.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/COUT.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 COUT " "Info: Found entity 1: COUT" {  } { { "COUT.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/COUT.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIFO_WRN_ByDSP.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FIFO_WRN_ByDSP.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fifo_wrn_bydsp-SYN " "Info: Found design unit 1: fifo_wrn_bydsp-SYN" {  } { { "FIFO_WRN_ByDSP.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/FIFO_WRN_ByDSP.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FIFO_WRN_ByDSP " "Info: Found entity 1: FIFO_WRN_ByDSP" {  } { { "FIFO_WRN_ByDSP.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/FIFO_WRN_ByDSP.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Freq_Divider_4.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Freq_Divider_4.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Freq_Divider_4-ARC " "Info: Found design unit 1: Freq_Divider_4-ARC" {  } { { "Freq_Divider_4.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/Freq_Divider_4.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Freq_Divider_4 " "Info: Found entity 1: Freq_Divider_4" {  } { { "Freq_Divider_4.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/Freq_Divider_4.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIFO_RDN_ByDSP.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file FIFO_RDN_ByDSP.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fifo_rdn_bydsp-SYN " "Info: Found design unit 1: fifo_rdn_bydsp-SYN" {  } { { "FIFO_RDN_ByDSP.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/FIFO_RDN_ByDSP.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 FIFO_RDN_ByDSP " "Info: Found entity 1: FIFO_RDN_ByDSP" {  } { { "FIFO_RDN_ByDSP.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/FIFO_RDN_ByDSP.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FPGA_DSP_PortLink.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file FPGA_DSP_PortLink.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FPGA_DSP_PortLink " "Info: Found entity 1: FPGA_DSP_PortLink" {  } { { "FPGA_DSP_PortLink.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FPGA_DSP_PortLink_Inner.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file FPGA_DSP_PortLink_Inner.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FPGA_DSP_PortLink_Inner " "Info: Found entity 1: FPGA_DSP_PortLink_Inner" {  } { { "FPGA_DSP_PortLink_Inner.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_Inner.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WSGN_MEGAFN_REPLACE" "MUX E:/ADFM/FPGA_DSP_PortLink/MUX.vhd " "Warning: Entity \"MUX\" obtained from \"E:/ADFM/FPGA_DSP_PortLink/MUX.vhd\" instead of from Quartus II megafunction library" {  } {  } 0 0 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus II megafunction library" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MUX.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file MUX.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 MUX-ARC " "Info: Found design unit 1: MUX-ARC" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 MUX " "Info: Found entity 1: MUX" {  } { { "MUX.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/MUX.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fifo_test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file fifo_test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 fifo_test " "Info: Found entity 1: fifo_test" {  } { { "fifo_test.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/fifo_test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "en_blk.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file en_blk.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 en_blk-ARC " "Info: Found design unit 1: en_blk-ARC" {  } { { "en_blk.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/en_blk.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 en_blk " "Info: Found entity 1: en_blk" {  } { { "en_blk.vhd" "" { Text "E:/ADFM/FPGA_DSP_PortLink/en_blk.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BiPort_Test.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file BiPort_Test.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BiPort_Test " "Info: Found entity 1: BiPort_Test" {  } { { "BiPort_Test.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/BiPort_Test.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 FPGA_DSP_PortLink_BiBus_oneFIFO " "Info: Found entity 1: FPGA_DSP_PortLink_BiBus_oneFIFO" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FPGA_DSP_PortLink_BiBus_oneFIFO " "Info: Elaborating entity \"FPGA_DSP_PortLink_BiBus_oneFIFO\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_bustri1 lpm_bustri1:inst4 " "Info: Elaborating entity \"lpm_bustri1\" for hierarchy \"lpm_bustri1:inst4\"" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "inst4" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 64 920 1040 120 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_bustri " "Info: Found entity 1: lpm_bustri" {  } { { "lpm_bustri.tdf" "" { Text "d:/program files/altera/quartus51/libraries/megafunctions/lpm_bustri.tdf" 29 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_bustri lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component " "Info: Elaborating entity \"lpm_bustri\" for hierarchy \"lpm_bustri1:inst4\|lpm_bustri:lpm_bustri_component\"" {  } { { "lpm_bustri1.vhd" "lpm_bustri_component" { Text "E:/ADFM/FPGA_DSP_PortLink/lpm_bustri1.vhd" 74 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "en_blk en_blk:inst8 " "Info: Elaborating entity \"en_blk\" for hierarchy \"en_blk:inst8\"" {  } { { "FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" "inst8" { Schematic "E:/ADFM/FPGA_DSP_PortLink/FPGA_DSP_PortLink_BiBus_oneFIFO.bdf" { { 360 136 312 456 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}