📄 uart_v.tcl
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########## Tcl recorder starts at 07/17/07 10:46:38 ##########
set version "6.1"
set proj_dir "F:/custmor training/Code test/2/1"
cd $proj_dir
# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
puts "File Open Error: $lsvini_path"
return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] {
set lline [string tolower $line]
set lline [string trim $lline]
if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
if {$path && [regexp {^\[} $lline]} {set path 0; break}
if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line; continue}
if {$path && [regexp {^fpgabinpath} $lline]} {set fpga_bin $line}}
set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]
set fpga_bin [string range $fpga_bin [expr [string first "=" $fpga_bin]+1] end]
regsub -all "\"" $fpga_bin "" fpga_bin
set fpga_bin [file join $fpga_bin]
if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
set env(PATH) "$fpga_bin;$env(PATH)" } }
if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
set env(PATH) "$cpld_bin;$env(PATH)" }
lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd
# Commands to make the Process:
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../../uart_verilog/uart.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_v.h"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../../uart_verilog/rcvr.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_v.h"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../../uart_verilog/txmit.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf xp.v -noglib -predefine uart_v.h"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
########## Tcl recorder end at 07/17/07 10:46:38 ###########
########## Tcl recorder starts at 07/17/07 10:47:36 ##########
set version "6.1"
set proj_dir "F:/custmor training/Code test/2/1"
cd $proj_dir
# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
puts "File Open Error: $lsvini_path"
return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] {
set lline [string tolower $line]
set lline [string trim $lline]
if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
if {$path && [regexp {^\[} $lline]} {set path 0; break}
if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line; continue}
if {$path && [regexp {^fpgabinpath} $lline]} {set fpga_bin $line}}
set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]
set fpga_bin [string range $fpga_bin [expr [string first "=" $fpga_bin]+1] end]
regsub -all "\"" $fpga_bin "" fpga_bin
set fpga_bin [file join $fpga_bin]
if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
set env(PATH) "$fpga_bin;$env(PATH)" } }
if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
set env(PATH) "$cpld_bin;$env(PATH)" }
lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd
# Commands to make the Process:
# Synplify Synthesize Verilog File
if [catch {open uart.cmd w} rspFile] {
puts stderr "Cannot create response file uart.cmd: $rspFile"
} else {
puts $rspFile "STYFILENAME: uart_v.sty
PROJECT: uart
WORKING_PATH: \"$proj_dir\"
MODULE: uart
VERILOG_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/verilog/XP.v\" uart_v.h ../../../uart_verilog/txmit.v ../../../uart_verilog/rcvr.v ../../../uart_verilog/uart.v
OUTPUT_FILE_NAME: uart
SUFFIX_NAME: edi
WRITE_PRF: false
Vlog_std_v2001: true
FREQUENCY: 200
FANOUT_LIMIT: 100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -3
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS: 3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS: 0
"
close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -rem -e uart -target LATTICE-XP -part LFXP3C"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete uart.cmd
########## Tcl recorder end at 07/17/07 10:47:36 ###########
########## Tcl recorder starts at 07/17/07 10:48:22 ##########
set version "6.1"
set proj_dir "F:/custmor training/Code test/2/1"
cd $proj_dir
# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
puts "File Open Error: $lsvini_path"
return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] {
set lline [string tolower $line]
set lline [string trim $lline]
if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
if {$path && [regexp {^\[} $lline]} {set path 0; break}
if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line; continue}
if {$path && [regexp {^fpgabinpath} $lline]} {set fpga_bin $line}}
set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]
set fpga_bin [string range $fpga_bin [expr [string first "=" $fpga_bin]+1] end]
regsub -all "\"" $fpga_bin "" fpga_bin
set fpga_bin [file join $fpga_bin]
if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
set env(PATH) "$fpga_bin;$env(PATH)" } }
if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
set env(PATH) "$cpld_bin;$env(PATH)" }
lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd
# Commands to make the Process:
# JEDEC Report
if [runCmd "\"$fpga_bin/edif2ngd\" -l mg5g00 -d LFXP3C \"uart.edi\" \"uart.ngo\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$fpga_bin/edfupdate\" -t \"uart_v.tcy\" -w \"uart.ngo\" -m \"uart.ngo\" \"uart_v.ngx\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$fpga_bin/ngdbuild\" -a mg5g00 -d LFXP3C -p \"$fpga_dir/mg5g00/data\" \"uart.ngo\" \"uart_v.ngd\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$fpga_bin/map\" -a mg5g00 -p LFXP3C -t TQFP100 -s 3 \"uart_v.ngd\" -o \"uart_v_map.ncd\" -mp \"uart_v.mrp\" \"uart_v.lpf\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [catch {open uart_v.cm2 w} rspFile] {
puts stderr "Cannot create response file uart_v.cm2: $rspFile"
} else {
puts $rspFile "-t uart_v.mt
-to uart_v.tw1
-o uart_v.tcm
-log uart_v.log
-pr uart_v.prf
-rpt uart_v.mrp
"
close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -m -f \"uart_v.cmm\" -f \"uart_v.cm2\" -arch mg5g00 \"uart_v_map.ncd\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete uart_v.cm2
if [catch {open uart_v.p2t w} rspFile] {
puts stderr "Cannot create response file uart_v.p2t: $rspFile"
} else {
puts $rspFile "-w
-i 6
-l 5
-n 1
-t 1
-s 1
-c 0
-e 0
-exp parPlcInLimit=0
-exp parPlcInNeighborSize=1
-exp parPathBased=OFF
-exp parHold=OFF
"
close $rspFile
}
if [catch {open uart_v.p3t w} rspFile] {
puts stderr "Cannot create response file uart_v.p3t: $rspFile"
} else {
puts $rspFile "-rem
-log uart_v.log
-o uart_v_mp.par
-pr uart_v.prf
"
close $rspFile
}
if [runCmd "\"$cpld_bin/multipar\" -p uart_v.p2t -f \"uart_v.p3t\" \"uart_v_map.ncd\" \"uart_v.ncd\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [catch {open uart_v.cm2 w} rspFile] {
puts stderr "Cannot create response file uart_v.cm2: $rspFile"
} else {
puts $rspFile "-t uart_v.pt
-to uart_v.twr
-o uart_v.tcp
-log uart_v.log
-pr uart_v.prf
-rpt uart_v.par
"
close $rspFile
}
if [runCmd "\"$cpld_bin/checkpoint\" -p -f \"uart_v.cmp\" -f \"uart_v.cm2\" -arch mg5g00 \"uart_v.ncd\" -l 60"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete uart_v.cm2
if [catch {open uart_v.t2b w} rspFile] {
puts stderr "Cannot create response file uart_v.t2b: $rspFile"
} else {
puts $rspFile "-g CfgMode:Disable
-g ReadBack:Flash
-g ReadCapture:Disable
-g RamCfg:Reset
-g SYNSRC:No
-g PllSET:None
-g ES:No
"
close $rspFile
}
if [runCmd "\"$fpga_bin/bitgen\" -f \"uart_v.t2b\" -w \"uart_v.ncd\" \"uart_v.prf\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
########## Tcl recorder end at 07/17/07 10:48:22 ###########
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