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synopsys.dc
/**********************************************************************/
/* */
/* File: synopsys.dc
synopsys.dc
/**********************************************************************/
/* */
/* File: synopsys.dc
cmpldes2.tcl
#
# Tcl script file for second part of Chapter 9
#
# Note: This script is run after the first compile completes.
#
# Remove any designs in memory
#
remove_design -all
#
# Read in the optimized design
xccpld_timesim.nlf
Release 7.1i - netgen H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim
xccpld.nga xccpld_timesim.vhd
Readin
xccpld.par_nlf
Release 7.1i - netgen H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim
xccpld.nga xccpld_timesim.vhd
Readin
crc_timesim.nlf
Release 7.1i - netgen H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Command Line: netgen -intstyle ise -s 4 -pcf crc.pcf -rpw 100 -tpw 0 -ar
Structure -xon true -w -ofmt vhdl -sim
crc_synthesis.nlf
Release 7.1i - netgen H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Command Line: netgen -intstyle ise -ar Structure -w -ofmt vhdl -sim crc.ngc
crc_synthesis.vhd
Reading design
crc.synth_nlf
Release 7.1i - netgen H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Command Line: netgen -intstyle ise -ar Structure -w -ofmt vhdl -sim crc.ngc
crc_synthesis.vhd
Reading design
crc.par_nlf
Release 7.1i - netgen H.38
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Command Line: netgen -intstyle ise -s 4 -pcf crc.pcf -rpw 100 -tpw 0 -ar
Structure -xon true -w -ofmt vhdl -sim
led.par_nlf
Release 7.1.04i - netgen H.42
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim
led.nga led_timesim.vhd
Reading d