crc_timesim.nlf

This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

Release 7.1i - netgen H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -s 4 -pcf crc.pcf -rpw 100 -tpw 0 -ar
Structure -xon true -w -ofmt vhdl -sim crc.ncd crc_timesim.vhd  

Read and Annotate design 'crc.ncd' ...
Loading device for application Rf_Device from file '3s400.nph' in environment
C:/Xilinx.
   "crc" is an NCD, version 3.1, device xc3s400, package ft256, speed -4
Loading constraints from 'crc.pcf'...
The speed grade (-4) differs from the speed grade specified in the .ncd file
(-4).
The number of routable networks is 17
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist 'crc_timesim.vhd' ...
Writing VHDL SDF file 'crc_timesim.sdf' ...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
   simulation primitives and has to be used with SIMPRIM library for correct
   compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 71664 kilobytes