crc.synth_nlf

This Circuit generates the syndrome for the CRC. This is quite useful for transmision purposes and e

Release 7.1i - netgen H.38
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.

Command Line: netgen -intstyle ise -ar Structure -w -ofmt vhdl -sim crc.ngc
crc_synthesis.vhd  

Reading design 'crc.ngc' ...
Flattening design ...
Processing design ... 
  Preping design's networks ...
  Preping design's macros ...
Writing VHDL netlist 'crc_synthesis.vhd' ...
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM library for correct
   compilation and simulation. 
Number of warnings: 0
Number of info messages: 1
Total memory usage is 44832 kilobytes