📄 led.par_nlf
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Release 7.1.04i - netgen H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Command Line: netgen -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim
led.nga led_timesim.vhd Reading design 'led.nga' ...Flattening design ...Processing design ... Preping design's networks ... Preping design's macros ...Writing VHDL netlist 'led_timesim.vhd' ...Writing VHDL SDF file 'led_timesim.sdf' ...INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
simulation primitives and has to be used with SIMPRIM library for correct
compilation and simulation. Number of warnings: 0Number of info messages: 1Total memory usage is 44204 kilobytes⌨️ 快捷键说明
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