synopsys.dc

xilinx官方PCIcore 有详细说明文档

/**********************************************************************/
/*                                                                    */
/* File:        synopsys.dc                                           */
/* Rev:         3.0.0                                                 */
/* Copyright (c) 2003 Xilinx, Inc.  All rights reserved.              */
/*                                                                    */
/**********************************************************************/


/* This is a script file for the Synopsys FPGA Compiler.  This script */
/* file shows how to compile the pcim_top example top-level design.   */
/* First, set up some information for use later.                      */

designer = "Xilinx LogiCORE Team"
company  = "Xilinx, Inc"


/* Read HDL design.  Analyze performs syntax checking, while          */
/* elaborate builds design with generic technology primitives.        */ 

analyze -format verilog ../../src/xpci/pci_lc_i.v
analyze -format verilog ../../src/xpci/pcim_lc.v
analyze -format verilog ../source/cfg_ping.v
analyze -format verilog ../source/ping.v
analyze -format verilog ../source/pcim_top.v

elaborate pcim_top > output.ela


/* Constrain user application. The constraints consist of a period    */
/* and additional constraints to specify route budgets between the    */
/* PCI interface and the user application.                            */

current_design "ping64"
create_clock "CLK" -period 15
set_output_delay 8 -clock "CLK" all_outputs()
set_max_delay 8 -from { "S_DATA", "S_SRC_EN", "S_DATA_VLD", \
                        "M_DATA", "M_SRC_EN", "M_DATA_VLD", \
                        "M_ADDR_N" } -to { "ADIO*" }


/* Compile the user application.  Once the compilation is complete,   */
/* set the dont_touch attribute on the PCI interface and the I/O      */
/* components in the pcim_lc module.  At this point, the user design  */
/* has already been compiled so dont_touch it either.  Insert any     */
/* pads required by the user application, then compile the design.    */

compile > output.com
current_design "pcim_lc"
set_dont_touch { "XPCI_*", "PCI_LC" }
current_design "pcim_top"
set_dont_touch "ping64"
set_port_is_pad { "PING_REQUEST64", "PING_REQUEST32", "PING_DONE" }
insert_pads
create_clock "PCLK" -period 15
compile


/* Perform some clean up by removing empty designs and setting        */
/* attributes before writing out the design files.                    */

remove_attribute "ping64" dont_touch
set_attribute find(design,"*") "xnfout_use_blknames" -type boolean false
remove_design "PCI_LC_I"


/* Write out the netlist in both EDIF and DB formats using the        */
/* hierarchy option.  Exit the Design Compiler.                       */

edifout_design_name = "pcim_top"
write -format db   -hierarchy -output "pcim_top.db"
write -format edif -hierarchy -output "pcim_top.sedif"
exit